statemachine1.vhd

来自「自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料」· VHDL 代码 · 共 60 行

---单进程状态机，我想做个比较，与双进程和三进程的状态机的区别。
--moore statemachine ,
--input 
--  reset
--  din
--output 
--  op
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
---------------------------------------------
entity statemachine1 is
  port( clk,reset,din: in std_logic;
        op: out std_logic
      );
end statemachine1;
-----------------------------------
architecture pyy of statemachine1 is
  type state is (s0,s1,s2,s3);    --state type declare;
  signal current_state : state;
--  signal next_state: state;
begin
	process(clk,reset,din)
	begin
		if reset='1'then
			current_state<=s0;
	    elsif rising_edge(clk) then
	    	current_state<=current_state;
	        case current_state is
				when s0=>	if  din='0' then
				            	current_state<=s0;
				            else
								current_state<=s1;
						    end if;
						    op<='0';
				when s1=>	if din='0' then
								current_state<=s2;
						    else 
						        current_state<=s1;
						    end if;
							op<='1';
				when s2=>	if  din='0' then
				            	current_state<=s3;
				            else
								current_state<=s2;
						    end if;
						    op<='0';
				when s3=>	if din='0' then
								current_state<=s1;
						    else 
						        current_state<=s0;
						    end if;
							op<='0';
			end case;
		end if;
	end process;
end pyy;