statemachine1.tan.rpt

自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料

; tsu                                                                     ;
+-------+--------------+------------+-------+------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To               ; To Clock ;
+-------+--------------+------------+-------+------------------+----------+
; N/A   ; None         ; 4.521 ns   ; din   ; current_state.s1 ; clk      ;
; N/A   ; None         ; 4.517 ns   ; din   ; current_state.s0 ; clk      ;
; N/A   ; None         ; 4.082 ns   ; din   ; current_state.s2 ; clk      ;
; N/A   ; None         ; 4.078 ns   ; din   ; current_state.s3 ; clk      ;
; N/A   ; None         ; 0.597 ns   ; reset ; op~reg0          ; clk      ;
+-------+--------------+------------+-------+------------------+----------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+---------+----+------------+
; Slack ; Required tco ; Actual tco ; From    ; To ; From Clock ;
+-------+--------------+------------+---------+----+------------+
; N/A   ; None         ; 7.205 ns   ; op~reg0 ; op ; clk        ;
+-------+--------------+------------+---------+----+------------+


+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+-------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To               ; To Clock ;
+---------------+-------------+-----------+-------+------------------+----------+
; N/A           ; None        ; -0.545 ns ; reset ; op~reg0          ; clk      ;
; N/A           ; None        ; -4.026 ns ; din   ; current_state.s3 ; clk      ;
; N/A           ; None        ; -4.030 ns ; din   ; current_state.s2 ; clk      ;
; N/A           ; None        ; -4.465 ns ; din   ; current_state.s0 ; clk      ;
; N/A           ; None        ; -4.469 ns ; din   ; current_state.s1 ; clk      ;
+---------------+-------------+-----------+-------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Jul 19 10:33:45 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off statemachine1 -c statemachine1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "current_state.s1" and destination register "op~reg0"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.495 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y11_N4; Fanout = 3; REG Node = 'current_state.s1'
            Info: 2: + IC(1.186 ns) + CELL(0.309 ns) = 1.495 ns; Loc. = LC_X2_Y9_N2; Fanout = 2; REG Node = 'op~reg0'
            Info: Total cell delay = 0.309 ns ( 20.67 % )
            Info: Total interconnect delay = 1.186 ns ( 79.33 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.768 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X2_Y9_N2; Fanout = 2; REG Node = 'op~reg0'
                Info: Total cell delay = 2.180 ns ( 78.76 % )
                Info: Total interconnect delay = 0.588 ns ( 21.24 % )
            Info: - Longest clock path from clock "clk" to source register is 2.768 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X2_Y11_N4; Fanout = 3; REG Node = 'current_state.s1'
                Info: Total cell delay = 2.180 ns ( 78.76 % )
                Info: Total interconnect delay = 0.588 ns ( 21.24 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "current_state.s1" (data pin = "din", clock pin = "clk") is 4.521 ns
    Info: + Longest pin to register delay is 7.252 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_5; Fanout = 4; PIN Node = 'din'
        Info: 2: + IC(5.045 ns) + CELL(0.738 ns) = 7.252 ns; Loc. = LC_X2_Y11_N4; Fanout = 3; REG Node = 'current_state.s1'
        Info: Total cell delay = 2.207 ns ( 30.43 % )
        Info: Total interconnect delay = 5.045 ns ( 69.57 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.768 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X2_Y11_N4; Fanout = 3; REG Node = 'current_state.s1'
        Info: Total cell delay = 2.180 ns ( 78.76 % )
        Info: Total interconnect delay = 0.588 ns ( 21.24 % )
Info: tco from clock "clk" to destination pin "op" through register "op~reg0" is 7.205 ns
    Info: + Longest clock path from clock "clk" to source register is 2.768 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X2_Y9_N2; Fanout = 2; REG Node = 'op~reg0'
        Info: Total cell delay = 2.180 ns ( 78.76 % )
        Info: Total interconnect delay = 0.588 ns ( 21.24 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.213 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y9_N2; Fanout = 2; REG Node = 'op~reg0'
        Info: 2: + IC(2.105 ns) + CELL(2.108 ns) = 4.213 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'op'
        Info: Total cell delay = 2.108 ns ( 50.04 % )
        Info: Total interconnect delay = 2.105 ns ( 49.96 % )
Info: th for register "op~reg0" (data pin = "reset", clock pin = "clk") is -0.545 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.768 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X2_Y9_N2; Fanout = 2; REG Node = 'op~reg0'
        Info: Total cell delay = 2.180 ns ( 78.76 % )
        Info: Total interconnect delay = 0.588 ns ( 21.24 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 3.328 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 5; PIN Node = 'reset'
        Info: 2: + IC(1.121 ns) + CELL(0.738 ns) = 3.328 ns; Loc. = LC_X2_Y9_N2; Fanout = 2; REG Node = 'op~reg0'
        Info: Total cell delay = 2.207 ns ( 66.32 % )
        Info: Total interconnect delay = 1.121 ns ( 33.68 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jul 19 10:33:46 2006
    Info: Elapsed time: 00:00:02