statemachine2.tan.rpt

自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料

; tsu                                                                    ;
+-------+--------------+------------+------+------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To               ; To Clock ;
+-------+--------------+------------+------+------------------+----------+
; N/A   ; None         ; 4.591 ns   ; din  ; current_state.s2 ; clk      ;
; N/A   ; None         ; 4.590 ns   ; din  ; current_state.s3 ; clk      ;
; N/A   ; None         ; 4.584 ns   ; din  ; current_state.s1 ; clk      ;
; N/A   ; None         ; 4.580 ns   ; din  ; current_state.s0 ; clk      ;
+-------+--------------+------------+------+------------------+----------+


+------------------------------------------------------------------------+
; tco                                                                    ;
+-------+--------------+------------+------------------+----+------------+
; Slack ; Required tco ; Actual tco ; From             ; To ; From Clock ;
+-------+--------------+------------+------------------+----+------------+
; N/A   ; None         ; 6.397 ns   ; current_state.s1 ; op ; clk        ;
+-------+--------------+------------+------------------+----+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To               ; To Clock ;
+---------------+-------------+-----------+------+------------------+----------+
; N/A           ; None        ; -4.528 ns ; din  ; current_state.s0 ; clk      ;
; N/A           ; None        ; -4.532 ns ; din  ; current_state.s1 ; clk      ;
; N/A           ; None        ; -4.538 ns ; din  ; current_state.s3 ; clk      ;
; N/A           ; None        ; -4.539 ns ; din  ; current_state.s2 ; clk      ;
+---------------+-------------+-----------+------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Jul 19 10:41:43 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off statemachine2 -c statemachine2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "current_state.s1" and destination register "current_state.s1"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.237 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y13_N3; Fanout = 3; REG Node = 'current_state.s1'
            Info: 2: + IC(0.759 ns) + CELL(0.478 ns) = 1.237 ns; Loc. = LC_X8_Y13_N3; Fanout = 3; REG Node = 'current_state.s1'
            Info: Total cell delay = 0.478 ns ( 38.64 % )
            Info: Total interconnect delay = 0.759 ns ( 61.36 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.768 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X8_Y13_N3; Fanout = 3; REG Node = 'current_state.s1'
                Info: Total cell delay = 2.180 ns ( 78.76 % )
                Info: Total interconnect delay = 0.588 ns ( 21.24 % )
            Info: - Longest clock path from clock "clk" to source register is 2.768 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X8_Y13_N3; Fanout = 3; REG Node = 'current_state.s1'
                Info: Total cell delay = 2.180 ns ( 78.76 % )
                Info: Total interconnect delay = 0.588 ns ( 21.24 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "current_state.s2" (data pin = "din", clock pin = "clk") is 4.591 ns
    Info: + Longest pin to register delay is 7.322 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_134; Fanout = 4; PIN Node = 'din'
        Info: 2: + IC(5.109 ns) + CELL(0.738 ns) = 7.322 ns; Loc. = LC_X8_Y13_N5; Fanout = 2; REG Node = 'current_state.s2'
        Info: Total cell delay = 2.213 ns ( 30.22 % )
        Info: Total interconnect delay = 5.109 ns ( 69.78 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.768 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X8_Y13_N5; Fanout = 2; REG Node = 'current_state.s2'
        Info: Total cell delay = 2.180 ns ( 78.76 % )
        Info: Total interconnect delay = 0.588 ns ( 21.24 % )
Info: tco from clock "clk" to destination pin "op" through register "current_state.s1" is 6.397 ns
    Info: + Longest clock path from clock "clk" to source register is 2.768 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X8_Y13_N3; Fanout = 3; REG Node = 'current_state.s1'
        Info: Total cell delay = 2.180 ns ( 78.76 % )
        Info: Total interconnect delay = 0.588 ns ( 21.24 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.405 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y13_N3; Fanout = 3; REG Node = 'current_state.s1'
        Info: 2: + IC(1.297 ns) + CELL(2.108 ns) = 3.405 ns; Loc. = PIN_133; Fanout = 0; PIN Node = 'op'
        Info: Total cell delay = 2.108 ns ( 61.91 % )
        Info: Total interconnect delay = 1.297 ns ( 38.09 % )
Info: th for register "current_state.s0" (data pin = "din", clock pin = "clk") is -4.528 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.768 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X8_Y13_N0; Fanout = 2; REG Node = 'current_state.s0'
        Info: Total cell delay = 2.180 ns ( 78.76 % )
        Info: Total interconnect delay = 0.588 ns ( 21.24 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.311 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_134; Fanout = 4; PIN Node = 'din'
        Info: 2: + IC(5.098 ns) + CELL(0.738 ns) = 7.311 ns; Loc. = LC_X8_Y13_N0; Fanout = 2; REG Node = 'current_state.s0'
        Info: Total cell delay = 2.213 ns ( 30.27 % )
        Info: Total interconnect delay = 5.098 ns ( 69.73 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jul 19 10:41:43 2006
    Info: Elapsed time: 00:00:01