📄 sm_module.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity sm_module is
port(
gclk_in : in std_logic;
clk_rx_in : in std_logic;
rx_offset : in std_logic_vector(12 downto 0);
sm_out : out std_logic_vector(18 downto 0);
sm_offset_out : out std_logic_vector(18 downto 0));
end sm_module;
architecture Behavioral of sm_module is
---------------------------------------------------------------------------------------------------
signal sm_flag : std_logic_vector(10 downto 0):="00000000000";
signal flag : std_logic:='0';
signal sm : std_logic_vector(18 downto 0):="0000000000000000000";
signal sm_offset : std_logic_vector(18 downto 0):="0000000000000000000";
begin
sm_out(18 downto 0) <= sm(18 downto 0);
sm_offset_out(18 downto 0) <= sm_offset(18 downto 0);
---------------------------------------------------------------------------------------------------
P_gen_sm_flag:process(gclk_in)
begin
if rising_edge(gclk_in) then
sm_flag(10 downto 0) <= sm_flag(10 downto 0) + 1;
if sm_flag(10 downto 0) = "11111111111" then
flag <= '1';
else
null;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
P_count1:process(gclk_in)
begin
if rising_edge(gclk_in) then
if flag = '0' then
sm(18 downto 0) <= "0000000000000000000";
elsif flag = '1' then
sm(18 downto 0) <= sm(18 downto 0) + 1;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
P_count2:process(clk_rx_in)
begin
if rising_edge(clk_rx_in) then
if flag = '0' then
sm_offset(18 downto 0) <= "0000000000000000000";
elsif flag = '1' then
sm_offset(18 downto 0) <= sm_offset(18 downto 0) + 1;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
end Behavioral;
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