top.vhd

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

use work.top_comp.all;

library UNISIM;
use UNISIM.VComponents.all;

entity top is
port(
--------------------------------------------Clock pins---------------------------------------------
		gclk_o	:	in	std_logic;			--60MHz	clock						
		gclk_b_N	:	in	std_logic;			--61.44MHz clock signal from rf3030
		gclk_b_P	:	in	std_logic;							
		clk_to_3020_N	:	out	std_logic;
		clk_to_3020_P	:	out	std_logic;
-------------------------------------------IQ_sel pins---------------------------------------------
		IQ_sel_3030_N	:	in		std_logic;
		IQ_sel_3030_P	:	in		std_logic;

--add for avoid non-normal 
		IQ_sel_3030_N_nouse	:	in		std_logic;
		IQ_sel_3030_P_nouse	:	in		std_logic;
--add end
		IQ_sel_3020_N	:	out	std_logic;
		IQ_sel_3020_P	:	out	std_logic;	
------------------------------------Data Pins between RF and FGPA----------------------------------							
		dfrom_3030_N	:	in		std_logic_vector(15 downto 0);		--code rate 61.44MHz,I、Q crossed	
		dfrom_3030_P	:	in		std_logic_vector(15 downto 0);	   
		dto_3020_N		:	out	std_logic_vector(15 downto 0);		--code rate 40.96MHz,I、Q crossed	
		dto_3020_P		:	out	std_logic_vector(15 downto 0);
		
		rf3020_aux_N		:	out	std_logic_vector(4 downto 0);							
		rf3020_aux_P		:	out	std_logic_vector(4 downto 0);
		rf3020_marker_N	:	out	std_logic_vector(4 downto 1);
		rf3020_marker_P	:	out	std_logic_vector(4 downto 1);

		rf3030_aux_N		:	in	std_logic_vector(4 downto 0);							
		rf3030_aux_P		:	in	std_logic_vector(4 downto 0);
		rf3030_marker_N	:	in	std_logic_vector(4 downto 1);
		rf3030_marker_P	:	in	std_logic_vector(4 downto 1);
-------------------------------------Pins between dsp and FGPA-----------------------------------
		dsp_fpga_data	:	inout	std_logic_vector(31 downto 0);
		dsp_fpga_addr	:	in		std_logic_vector(20 downto 3);
		dsp_fpga_clk		:	in		std_logic;	
		dsp_fpga_we	:	in	std_logic;
		dsp_fpga_oe	:	in	std_logic;
		dsp_fpga_ce1	:	in	std_logic;		
		dsp_fpga_ext_int4	:	out std_logic;
		dsp_fpga_ext_int5	:	out std_logic;
		dsp_fpga_ext_int6	:	out std_logic;
		dsp_fpga_ext_int7	:	out std_logic;

		led	:	out	std_logic_vector(3 downto 0));
end top;

architecture Behavioral of top is

signal	S_gclk_b	:	std_logic;

signal	S_sm	:	std_logic_vector(18 downto 0);
signal	S_sm_offset	:	std_logic_vector(18 downto 0);

signal	S_rf3030_I	:	std_logic_vector(15 downto 0);
signal	S_rf3030_Q	:	std_logic_vector(15 downto 0);	

signal	S_dsp_din		:	std_logic_vector(31 downto 0);
signal	S_dsp_dout	:	std_logic_vector(31 downto 0);
signal	S_rx_offset	:	std_logic_vector(12 downto 0);

begin
	
led(3)	<=	S_sm(18);
led(1)	<=	S_sm_offset(18);
led(0)	<=	S_sm_offset(17);
-------------------------------------------SM PORT MAP------------------------------------------
U_sm_top : sm_module
port	map(
		gclk_in		=>	gclk_o,
		clk_rx_in	=>	S_gclk_b,			
		rx_offset	=>	S_rx_offset(12 downto 0),
		sm_out		=>	S_sm(18 downto 0),
		sm_offset_out	=>  S_sm_offset(18 downto 0));		
---------------------------------------RF3030 PORT MAP------------------------------------------
U_rf3030_rx	:	rf3030_module
port	map(					
		gclk_b_N_in		=>	gclk_b_N,		--61.44MHz clock signal from rf3030
		gclk_b_P_in		=>	gclk_b_P,			
		gclk_b_out		=>	S_gclk_b,	
		IQ_sel_rf3030_N_in	=>	IQ_sel_3030_N,
		IQ_sel_rf3030_P_in	=>	IQ_sel_3030_P,	
		IQ_sel_3030_N_nouse	=>	IQ_sel_3030_N_nouse,
		IQ_sel_3030_P_nouse	=>	IQ_sel_3030_P_nouse,
		Rf3030_aux_N			=>	rf3030_aux_N(4 downto 0),							
		Rf3030_aux_P			=>	rf3030_aux_P(4 downto 0),
		Rf3030_marker_N		=>	rf3030_marker_N(4 downto 1),
		Rf3030_marker_P		=>	rf3030_marker_P(4 downto 1),				
		data_from_rf3030_N_in	=>	dfrom_3030_N(15 downto 0),	--code rate 61.44MHz,I、Q crossed		
		data_from_rf3030_P_in	=>	dfrom_3030_P(15 downto 0),	
		data_rx_I	=>	S_rf3030_I(15 downto 0),	   			
		data_rx_Q	=>	S_rf3030_Q(15 downto 0),
		test		=> led(2));
---------------------------------------------------------------------------------------------------
P_latch_rx_in	:	process(S_gclk_b)	--物理层数据输入至DSP	  		
begin
if rising_edge(S_gclk_b)	then				 
	S_dsp_din(15 downto 0)		<=	S_rf3030_I(15 downto 0);	--!!!!!!!!!!!!!!!!!!!!!!!	
	S_dsp_din(31 downto 16)		<=	S_rf3030_Q(15 downto 0);	
end if;
end process;
---------------------------------------------------------------------------------------------------
-----------------------------------------dsp_RAM PORT MAP----------------------------------------
U_dsp_ram_top : dsp_ram_module
port	map(
		dsp_fpga_data		=>	dsp_fpga_data(31 downto 0),
		dsp_fpga_addr		=>	dsp_fpga_addr(20 downto 3),
		dsp_fpga_clk		=>	dsp_fpga_clk,
		dsp_fpga_we			=>	dsp_fpga_we,
		dsp_fpga_oe			=>	dsp_fpga_oe,
		dsp_fpga_ce1		=>	dsp_fpga_ce1,
		dsp_fpga_ext_int4	=>	dsp_fpga_ext_int4,
		dsp_fpga_ext_int5	=>	dsp_fpga_ext_int5,
		dsp_fpga_ext_int6	=>	dsp_fpga_ext_int6,
		dsp_fpga_ext_int7	=>	dsp_fpga_ext_int7,
		gclk_o	=>	gclk_o,	
		clk_rx	=>	S_gclk_b,	
		addr_tx	=>	S_sm(16 downto 4),
		addr_rx	=>	S_sm_offset(14 downto 2),
		rx_offset_out		=>	S_rx_offset(12 downto 0),
		dsp_ram_rx_dina	=>	S_dsp_din(31 downto 0),	 			--ram_rx A port input data bus		
		dsp_ram_tx_douta=>	S_dsp_dout(31 downto 0));			--ram_tx A port output data bus													
-----------------------------------------RF3020 PORT MAP----------------------------------------
U_intf : rf3020_module
port map (
			gclk_in		=> gclk_o,
			sm				=>	S_sm(2 downto 0),
			din_I			=>	S_dsp_dout(15 downto 0),
			din_Q			=>	S_dsp_dout(31 downto 16), 
			dout_p		=>	dto_3020_P(15 downto 0),
			dout_n		=>	dto_3020_N(15 downto 0),   
			clk_8x_p	=>	clk_to_3020_P, 
			clk_8x_n	=>	clk_to_3020_N,
			sel_iq_p	=>	IQ_sel_3020_P,  
			sel_iq_n	=>	IQ_sel_3020_N,
			aux_N			=>	rf3020_aux_N(4 downto 0),
			aux_P			=>	rf3020_aux_P(4 downto 0),
			marker_N	=>	rf3020_marker_N(4 downto 1),
			marker_P	=>	rf3020_marker_P(4 downto 1));			
-----------------------------------------------------------------------------------------------
end Behavioral;