rf3030_module.vhd

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity rf3030_module is
port(
--------------------------------------------Clock pins---------------------------------------------						
		gclk_b_N_in	:	in	std_logic;			--61.44MHz clock signal from rf3030
		gclk_b_P_in	:	in	std_logic;			
		
		gclk_b_out	:	out	std_logic;	
-------------------------------------------IQ_sel pins---------------------------------------------
		IQ_sel_rf3030_N_in	:	in	std_logic;
		IQ_sel_rf3030_P_in	:	in	std_logic;

		IQ_sel_3030_N_nouse	:	in		std_logic;
		IQ_sel_3030_P_nouse	:	in		std_logic;

		Rf3030_aux_N		:	in	std_logic_vector(4 downto 0);							
		Rf3030_aux_P		:	in	std_logic_vector(4 downto 0);
		Rf3030_marker_N	:	in	std_logic_vector(4 downto 1);
		Rf3030_marker_P	:	in	std_logic_vector(4 downto 1);
------------------------------------Data Pins between RF and FGPA----------------------------------							
		data_from_rf3030_N_in	:	in	std_logic_vector(15 downto 0);	--code rate 61.44MHz,I、Q crossed	
		data_from_rf3030_P_in	:	in	std_logic_vector(15 downto 0);
---------------------------------------------------------------------------------------------------
		data_rx_I	:	out	std_logic_vector(15 downto 0);	   			
		data_rx_Q	:	out	std_logic_vector(15 downto 0);
		test			:	out	std_logic);
end rf3030_module;

architecture Behavioral of rf3030_module is
component IBUFGDS_LVDS_25				--clock in buffer
	port(
	I		: in  std_logic;
	IB  : in  std_logic;
	O   : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
component	IBUFDS_LVDS_25 				--data in buffer
	port(
	O 	:	out std_logic; 
  I 	:	in 	std_logic;  
  IB 	:	in	std_logic);
end component;
---------------------------------------------------------------------------------------------------
signal	gclk_b	:	std_logic;

signal	IQ_sel_rf3030			:	std_logic:='0';
signal	IQ_sel_rf3030_reg	:	std_logic:='0';

signal	data_from_rf3030	:	std_logic_vector(15 downto 0):=x"0000";	
signal	data_from_rf3030_reg:	std_logic_vector(15 downto 0):=x"0000";	

signal	data_sel_I			:	std_logic_vector(15 downto 0):=x"0000";			 --Demux data signal
signal	data_sel_I_reg	:	std_logic_vector(15 downto 0):=x"0000";	
signal	data_sel_I_reg2	:	std_logic_vector(15 downto 0):=x"0000";	
signal	data_sel_Q			:	std_logic_vector(15 downto 0):=x"0000";	
signal	data_sel_Q_reg			:	std_logic_vector(15 downto 0):=x"0000";	

signal	r3030_aux		:	std_logic_vector(4 downto 0);	
signal	r3030_marker	:	std_logic_vector(4 downto 1);
signal	iq_nouse	:std_logic;

begin
---------------------------------------------------------------------------------------------------
U_global_b: IBUFGDS_LVDS_25
port map (
	I => gclk_b_P_in,
	IB => gclk_b_N_in,
	O => gclk_b);
---------------------------------------------------------------------------------------------------
U_IQ_sel_rf3030: IBUFDS_LVDS_25
port map (
	O => IQ_sel_rf3030,
	I => IQ_sel_rf3030_P_in,
	IB => IQ_sel_rf3030_N_in);

U_IQ_sel_nouse: IBUFDS_LVDS_25
port map (
	O => iq_nouse,
	I => IQ_sel_3030_P_nouse,
	IB => IQ_sel_3030_N_nouse);
---------------------------------------------------------------------------------------------------
G_rf3030_data: for i in 0 to 15 generate
	 U_rf3030_data : IBUFDS_LVDS_25
   port map (
      O =>  data_from_rf3030(i),
      I =>  data_from_rf3030_P_in(i),
      IB => data_from_rf3030_N_in(i));
end	generate;
---------------------------------------------------------------------------------------------------
G_rf3030_aux: for i in 0 to 4 generate
	 U_rf3030_aux : IBUFDS_LVDS_25
   port map (
      O =>  r3030_aux(i),
      I =>  Rf3030_aux_P(i),
      IB => Rf3030_aux_N(i));
end	generate;
---------------------------------------------------------------------------------------------------
G_rf3030_marker: for i in 1 to 4 generate
	 U_rf3030_marker : IBUFDS_LVDS_25
   port map (
      O =>  r3030_marker(i),
      I =>  Rf3030_marker_P(i),
      IB => Rf3030_marker_N(i));
end	generate;
---------------------------------------------------------------------------------------------------
P_latch:process(gclk_b)					--latch one clock to make data stable
begin
if falling_edge(gclk_b)	then
	data_from_rf3030_reg(15 downto 0) <= data_from_rf3030(15 downto 0);
	IQ_sel_rf3030_reg	<=	IQ_sel_rf3030;
end if;
end process;
---------------------------------------------------------------------------------------------------
P_data_demux:process(gclk_b)		--dumux the I\Q signal
begin
if rising_edge(gclk_b)	then
	if IQ_sel_rf3030_reg = '1'	then
		data_sel_I(15 downto 0) <= data_from_rf3030_reg(15 downto 0);
	elsif	IQ_sel_rf3030_reg = '0'	then 
	  data_sel_Q(15 downto 0) <= data_from_rf3030_reg(15 downto 0);
	else	
		null;
	end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
P_data_align:process(gclk_b)
begin
if rising_edge(gclk_b)	then
	data_sel_I_reg(15 downto 0) 	<= data_sel_I(15 downto 0);			
	data_sel_I_reg2(15 downto 0) 	<= data_sel_I_reg(15 downto 0);	
	data_sel_Q_reg(15 downto 0) 	<= data_sel_Q(15 downto 0);	
end if;																											
end process;	
---------------------------------------------------------------------------------------------------
data_rx_I(15 downto 0)	<=	data_sel_I_reg2(15 downto 0);	   			
data_rx_Q(15 downto 0)	<=	data_sel_Q_reg(15 downto 0);

gclk_b_out	<=	gclk_b;

test	<=	iq_nouse or r3030_aux(0) or r3030_aux(1) or r3030_aux(2)	 or r3030_aux(3) or r3030_aux(4)				
			or r3030_marker(1) or r3030_marker(2) or r3030_marker(3) or r3030_marker(4);
end Behavioral;