rf3020_module.vhd

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity rf3020_module is
port (
			gclk_in		:	in	std_logic;
			sm				:	in	std_logic_vector(2 downto 0);
			din_I			:	in	std_logic_vector(15 downto 0);
			din_Q			: in std_logic_vector(15 downto 0);
			dout_p    : out std_logic_vector(15 downto 0);
			dout_n    : out std_logic_vector(15 downto 0);
			clk_8x_p 	: out std_logic;
			clk_8x_n 	: out std_logic;
			sel_iq_p  : out std_logic;
			sel_iq_n  : out std_logic;
			aux_N			:	out	std_logic_vector(4 downto 0);
			aux_P			:	out	std_logic_vector(4 downto 0);
			marker_N	:	out	std_logic_vector(4 downto 1);
			marker_P	:	out	std_logic_vector(4 downto 1));
end rf3020_module;

architecture Behavioral of rf3020_module is

component	OBUFDS_LVDS_25 		
	port(
  O 	:	out std_logic;  
  OB 	:	out	std_logic;
	I 	:	in 	std_logic);
end component;

signal	af3020_iqsel	:	std_logic;
signal	af3020_clk		:	std_logic;

signal	dout			:	std_logic_vector(15 downto 0);	

begin
---------------------------------------------------------------------------------------------------	
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P_iqmux:process(gclk_in)
begin
if rising_edge(gclk_in)	then
	if	sm(2 downto 0) = "000" then
		dout(15 downto 0)	<=	din_I(15 downto 0);
	elsif	 sm(2 downto 0) = "100" then
		dout(15 downto 0)	<=	din_Q(15 downto 0);
	else
		null;
	end if;
end if;
end process;
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P_gen_3020_iqsel:process(gclk_in)
begin
if rising_edge(gclk_in)	then
	if	sm(2 downto 0) = "000" then
		af3020_iqsel	<=	'1';
	elsif	 sm(2 downto 0) = "100" then
		af3020_iqsel	<=	'0';
	else
		null;
	end if;
end if;
end process;
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P_gen_3020_clk:process(gclk_in)
begin
if rising_edge(gclk_in)	then
	if	sm(2 downto 0) = "000" or	sm(2 downto 0) = "100"	then
		af3020_clk	<=	'0';
	elsif	sm(2 downto 0) = "010" or	sm(2 downto 0) = "110"	then 
		af3020_clk	<=	'1';
	else
		null;
	end if;
end if;
end process;
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G_rf3020: for j in 0 to 15 generate
	 U_rf3020_data : OBUFDS_LVDS_25
   port map (
      O => 	dout_p(j), 
      OB => dout_n(j),
      I => 	dout(j));
end	generate;

U_IQ_sel: OBUFDS_LVDS_25
	port map(
  O  =>	sel_iq_p,
  OB =>	sel_iq_n,
	I  =>	af3020_iqsel);

U_clk: OBUFDS_LVDS_25
	port map(
  O  =>	clk_8x_p,
  OB =>	clk_8x_n,
	I  =>	af3020_clk);

G_aux: for m in 0 to 4 generate
	 U_rf3020_aux : OBUFDS_LVDS_25
   port map (
      O => 	aux_P(m), 
      OB => aux_N(m),
      I => 	'0');
end	generate;

G_marker: for n in 1 to 4 generate
	 U_rf3020_marker : OBUFDS_LVDS_25
   port map (
      O => 	marker_P(n), 
      OB => marker_N(n),
      I => 	'0');
end	generate;
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end Behavioral;