📄 mfreq.vhd
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LIBRARY IEEE;---库文件
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mfreq IS ---实体
PORT(
clk, spken: IN STD_LOGIC;
q: IN INTEGER RANGE 0 TO 7;
spk: OUT STD_LOGIC);
END mfreq;
ARCHITECTURE beha OF mfreq IS ---结构体
SIGNAL fullspks: STD_LOGIC;
SIGNAL divfrq: INTEGER RANGE 0 TO 7643;
BEGIN
PROCESS(q)---进程语句1
BEGIN
CASE q IS
WHEN 0 =>divfrq<= 7643;------key0(do)
WHEN 1 =>divfrq<= 6809;------key1(re)
WHEN 2 =>divfrq<= 6066;------key2(mi)
WHEN 3 =>divfrq<= 5725;------key3(fa)
WHEN 4 =>divfrq<= 5101;------key4(sol)
WHEN 5 =>divfrq<= 4544;------key5(la)
WHEN 6 =>divfrq<= 4048;------key6(si)
WHEN 7 =>divfrq<= 3022;------key7(!do)
END case;
END PROCESS;
PROCESS(clk)----进程语句2
VARIABLE count13 : INTEGER RANGE 0 TO 7643;
BEGIN
IF (clk'EVENT AND clk='1')THEN
IF spken='1' THEN
IF count13=divfrq THEN
count13:=0;
fullspks<='0';
ELSE
count13:=count13+1;
fullspks<='1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(fullspks)----进程语句3
VARIABLE count2:STD_LOGIC;
BEGIN
IF (fullspks 'EVENT AND fullspks='1')THEN
count2:= NOT count2;
spk <= count2;
END IF;
END PROCESS;
END beha;
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