example.map.qmsg

这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 17 09:22:44 2006 " "Info: Processing started: Mon Jul 17 09:22:44 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off example -c example " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off example -c example" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keyncode.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file keyncode.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 keyncode-beha " "Info: Found design unit 1: keyncode-beha" {  } { { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 keyncode " "Info: Found entity 1: keyncode" {  } { { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mfreq.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file mfreq.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mfreq-beha " "Info: Found design unit 1: mfreq-beha" {  } { { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 mfreq " "Info: Found entity 1: mfreq" {  } { { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "example.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file example.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 example " "Info: Found entity 1: example" {  } { { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "example " "Info: Elaborating entity \"example\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mfreq mfreq:inst3 " "Info: Elaborating entity \"mfreq\" for hierarchy \"mfreq:inst3\"" {  } { { "example.bdf" "inst3" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 112 424 520 208 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "keyncode keyncode:inst1 " "Info: Elaborating entity \"keyncode\" for hierarchy \"keyncode:inst1\"" {  } { { "example.bdf" "inst1" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 112 216 344 208 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "mfreq:inst3\|count13\[0\]~13 13 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=13) from the following logic: \"mfreq:inst3\|count13\[0\]~13\"" {  } { { "mfreq.vhd" "count13\[0\]~13" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 32 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "mfreq:inst3\|count2 mfreq:inst3\|spk " "Info: Duplicate register \"mfreq:inst3\|count2\" merged to single register \"mfreq:inst3\|spk\"" {  } { { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 46 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "keyncode:inst1\|q\[1\] " "Warning: Latch keyncode:inst1\|q\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA key\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal key\[5\]" {  } { { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 136 24 192 152 "key\[7..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 13 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "keyncode:inst1\|q\[0\] " "Warning: Latch keyncode:inst1\|q\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA key\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal key\[0\]" {  } { { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 136 24 192 152 "key\[7..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 13 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "keyncode:inst1\|q\[2\] " "Warning: Latch keyncode:inst1\|q\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA key\[0\] " "Warning: Ports D and ENA on the latch are fed by the same signal key\[0\]" {  } { { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 136 24 192 152 "key\[7..0\]" "" } } } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 13 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "52 " "Info: Implemented 52 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "42 " "Info: Implemented 42 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 17 09:22:48 2006 " "Info: Processing ended: Mon Jul 17 09:22:48 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}