example.tan.qmsg

来自「这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需」· QMSG 代码 · 共 17 行 · 第 1/4 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "mfreq:inst3\|fullspks " "Info: Detected ripple clock \"mfreq:inst3\|fullspks\" as buffer" {  } { { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "mfreq:inst3\|fullspks" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] register mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 59.17 MHz 16.9 ns Internal " "Info: Clock \"clk\" has Internal fmax of 59.17 MHz between source register \"mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]\" and destination register \"mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" (period= 16.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.400 ns + Longest register register " "Info: + Longest register to register delay is 14.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 1 REG LC2_C11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C11; Fanout = 3; REG Node = 'mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.600 ns) 2.700 ns mfreq:inst3\|Equal~485 2 COMB LC2_C10 1 " "Info: 2: + IC(1.100 ns) + CELL(1.600 ns) = 2.700 ns; Loc. = LC2_C10; Fanout = 1; COMB Node = 'mfreq:inst3\|Equal~485'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "2.700 ns" { mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] mfreq:inst3|Equal~485 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.200 ns rtl~208 3 COMB LC3_C10 1 " "Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 5.200 ns; Loc. = LC3_C10; Fanout = 1; COMB Node = 'rtl~208'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "2.500 ns" { mfreq:inst3|Equal~485 rtl~208 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.400 ns) 8.700 ns rtl~193 4 COMB LC1_C12 2 " "Info: 4: + IC(1.100 ns) + CELL(2.400 ns) = 8.700 ns; Loc. = LC1_C12; Fanout = 2; COMB Node = 'rtl~193'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "3.500 ns" { rtl~208 rtl~193 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.200 ns) 12.000 ns mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[12\]~1 5 COMB LC8_C11 14 " "Info: 5: + IC(1.100 ns) + CELL(2.200 ns) = 12.000 ns; Loc. = LC8_C11; Fanout = 14; COMB Node = 'mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[12\]~1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "3.300 ns" { rtl~193 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 14.400 ns mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 6 REG LC3_C9 3 " "Info: 6: + IC(1.000 ns) + CELL(1.400 ns) = 14.400 ns; Loc. = LC3_C9; Fanout = 3; REG Node = 'mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "2.400 ns" { mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.100 ns ( 70.14 % ) " "Info: Total cell delay = 10.100 ns ( 70.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 29.86 % ) " "Info: Total interconnect delay = 4.300 ns ( 29.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "14.400 ns" { mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] mfreq:inst3|Equal~485 rtl~208 rtl~193 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "14.400 ns" { mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] mfreq:inst3|Equal~485 rtl~208 rtl~193 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 1.100ns 0.000ns 1.100ns 1.100ns 1.000ns } { 0.000ns 1.600ns 2.500ns 2.400ns 2.200ns 1.400ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_79 15 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 15; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { clk } "NODE_NAME" } "" } } { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 64 24 192 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 5.300 ns mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC3_C9 3 " "Info: 2: + IC(3.300 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C9; Fanout = 3; REG Node = 'mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "3.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 37.74 % ) " "Info: Total cell delay = 2.000 ns ( 37.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 62.26 % ) " "Info: Total interconnect delay = 3.300 ns ( 62.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_79 15 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 15; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { clk } "NODE_NAME" } "" } } { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 64 24 192 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 5.300 ns mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\] 2 REG LC2_C11 3 " "Info: 2: + IC(3.300 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_C11; Fanout = 3; REG Node = 'mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "3.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 37.74 % ) " "Info: Total cell delay = 2.000 ns ( 37.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 62.26 % ) " "Info: Total interconnect delay = 3.300 ns ( 62.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.800 ns + " "Info: + Micro clock to output delay of source is 0.800 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.700 ns + " "Info: + Micro setup delay of destination is 1.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "14.400 ns" { mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] mfreq:inst3|Equal~485 rtl~208 rtl~193 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "14.400 ns" { mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] mfreq:inst3|Equal~485 rtl~208 rtl~193 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 1.100ns 0.000ns 1.100ns 1.100ns 1.000ns } { 0.000ns 1.600ns 2.500ns 2.400ns 2.200ns 1.400ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] key\[3\] clk 29.600 ns register " "Info: tsu for register \"mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]\" (data pin = \"key\[3\]\", clock pin = \"clk\") is 29.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "33.200 ns + Longest pin register " "Info: + Longest pin to register delay is 33.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 5.000 ns key\[3\] 1 PIN PIN_45 4 " "Info: 1: + IC(0.000 ns) + CELL(5.000 ns) = 5.000 ns; Loc. = PIN_45; Fanout = 4; PIN Node = 'key\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { key[3] } "NODE_NAME" } "" } } { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 136 24 192 152 "key\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.400 ns) 10.000 ns keyncode:inst1\|spken~258 2 COMB LC4_C3 1 " "Info: 2: + IC(2.600 ns) + CELL(2.400 ns) = 10.000 ns; Loc. = LC4_C3; Fanout = 1; COMB Node = 'keyncode:inst1\|spken~258'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.000 ns" { key[3] keyncode:inst1|spken~258 } "NODE_NAME" } "" } } { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.400 ns) 12.600 ns keyncode:inst1\|spken~254 3 COMB LC5_C3 1 " "Info: 3: + IC(0.200 ns) + CELL(2.400 ns) = 12.600 ns; Loc. = LC5_C3; Fanout = 1; COMB Node = 'keyncode:inst1\|spken~254'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "2.600 ns" { keyncode:inst1|spken~258 keyncode:inst1|spken~254 } "NODE_NAME" } "" } } { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.400 ns) 15.200 ns keyncode:inst1\|spken~279 4 COMB LC8_C3 36 " "Info: 4: + IC(0.200 ns) + CELL(2.400 ns) = 15.200 ns; Loc. = LC8_C3; Fanout = 36; COMB Node = 'keyncode:inst1\|spken~279'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "2.600 ns" { keyncode:inst1|spken~254 keyncode:inst1|spken~279 } "NODE_NAME" } "" } } { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.600 ns) 18.800 ns keyncode:inst1\|q\[1\] 5 COMB LOOP LC8_C10 12 " "Info: 5: + IC(0.000 ns) + CELL(3.600 ns) = 18.800 ns; Loc. = LC8_C10; Fanout = 12; COMB LOOP Node = 'keyncode:inst1\|q\[1\]'" { { "Info" "ITDB_PART_OF_SCC" "keyncode:inst1\|q\[1\] LC8_C10 " "Info: Loc. = LC8_C10; Node \"keyncode:inst1\|q\[1\]\"" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { keyncode:inst1|q[1] } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { keyncode:inst1|q[1] } "NODE_NAME" } "" } } { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 13 -1 0 } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "3.600 ns" { keyncode:inst1|spken~279 keyncode:inst1|q[1] } "NODE_NAME" } "" } } { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.400 ns) 22.300 ns rtl~191 6 COMB LC5_C12 1 " "Info: 6: + IC(1.100 ns) + CELL(2.400 ns) = 22.300 ns; Loc. = LC5_C12; Fanout = 1; COMB Node = 'rtl~191'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "3.500 ns" { keyncode:inst1|q[1] rtl~191 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.400 ns) 24.900 ns rtl~192 7 COMB LC8_C12 1 " "Info: 7: + IC(0.200 ns) + CELL(2.400 ns) = 24.900 ns; Loc. = LC8_C12; Fanout = 1; COMB Node = 'rtl~192'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "2.600 ns" { rtl~191 rtl~192 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.400 ns) 27.500 ns rtl~193 8 COMB LC1_C12 2 " "Info: 8: + IC(0.200 ns) + CELL(2.400 ns) = 27.500 ns; Loc. = LC1_C12; Fanout = 2; COMB Node = 'rtl~193'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "2.600 ns" { rtl~192 rtl~193 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.200 ns) 30.800 ns mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[12\]~1 9 COMB LC8_C11 14 " "Info: 9: + IC(1.100 ns) + CELL(2.200 ns) = 30.800 ns; Loc. = LC8_C11; Fanout = 14; COMB Node = 'mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|counter_cell\[12\]~1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "3.300 ns" { rtl~193 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 311 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 33.200 ns mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] 10 REG LC8_C9 3 " "Info: 10: + IC(1.000 ns) + CELL(1.400 ns) = 33.200 ns; Loc. = LC8_C9; Fanout = 3; REG Node = 'mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "2.400 ns" { mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "26.600 ns ( 80.12 % ) " "Info: Total cell delay = 26.600 ns ( 80.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.600 ns ( 19.88 % ) " "Info: Total interconnect delay = 6.600 ns ( 19.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "33.200 ns" { key[3] keyncode:inst1|spken~258 keyncode:inst1|spken~254 keyncode:inst1|spken~279 keyncode:inst1|q[1] rtl~191 rtl~192 rtl~193 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "33.200 ns" { key[3] key[3]~out keyncode:inst1|spken~258 keyncode:inst1|spken~254 keyncode:inst1|spken~279 keyncode:inst1|q[1] rtl~191 rtl~192 rtl~193 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 2.600ns 0.200ns 0.200ns 0.000ns 1.100ns 0.200ns 0.200ns 1.100ns 1.000ns } { 0.000ns 5.000ns 2.400ns 2.400ns 2.400ns 3.600ns 2.400ns 2.400ns 2.400ns 2.200ns 1.400ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.700 ns + " "Info: + Micro setup delay of destination is 1.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_79 15 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 15; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { clk } "NODE_NAME" } "" } } { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 64 24 192 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 5.300 ns mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] 2 REG LC8_C9 3 " "Info: 2: + IC(3.300 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_C9; Fanout = 3; REG Node = 'mfreq:inst3\|lpm_counter:count13_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "3.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 37.74 % ) " "Info: Total cell delay = 2.000 ns ( 37.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 62.26 % ) " "Info: Total interconnect delay = 3.300 ns ( 62.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "33.200 ns" { key[3] keyncode:inst1|spken~258 keyncode:inst1|spken~254 keyncode:inst1|spken~279 keyncode:inst1|q[1] rtl~191 rtl~192 rtl~193 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "33.200 ns" { key[3] key[3]~out keyncode:inst1|spken~258 keyncode:inst1|spken~254 keyncode:inst1|spken~279 keyncode:inst1|q[1] rtl~191 rtl~192 rtl~193 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[12]~1 mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 2.600ns 0.200ns 0.200ns 0.000ns 1.100ns 0.200ns 0.200ns 1.100ns 1.000ns } { 0.000ns 5.000ns 2.400ns 2.400ns 2.400ns 3.600ns 2.400ns 2.400ns 2.400ns 2.200ns 1.400ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.300 ns" { clk mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk spk mfreq:inst3\|spk 16.500 ns register " "Info: tco from clock \"clk\" to destination pin \"spk\" through register \"mfreq:inst3\|spk\" is 16.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_79 15 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 15; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { clk } "NODE_NAME" } "" } } { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 64 24 192 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.800 ns) 6.100 ns mfreq:inst3\|fullspks 2 REG LC1_C10 1 " "Info: 2: + IC(3.300 ns) + CELL(0.800 ns) = 6.100 ns; Loc. = LC1_C10; Fanout = 1; REG Node = 'mfreq:inst3\|fullspks'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "4.100 ns" { clk mfreq:inst3|fullspks } "NODE_NAME" } "" } } { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.000 ns) 10.100 ns mfreq:inst3\|spk 3 REG LC4_C23 2 " "Info: 3: + IC(4.000 ns) + CELL(0.000 ns) = 10.100 ns; Loc. = LC4_C23; Fanout = 2; REG Node = 'mfreq:inst3\|spk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "4.000 ns" { mfreq:inst3|fullspks mfreq:inst3|spk } "NODE_NAME" } "" } } { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 27.72 % ) " "Info: Total cell delay = 2.800 ns ( 27.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.300 ns ( 72.28 % ) " "Info: Total interconnect delay = 7.300 ns ( 72.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "10.100 ns" { clk mfreq:inst3|fullspks mfreq:inst3|spk } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clk clk~out mfreq:inst3|fullspks mfreq:inst3|spk } { 0.000ns 0.000ns 3.300ns 4.000ns } { 0.000ns 2.000ns 0.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.800 ns + " "Info: + Micro clock to output delay of source is 0.800 ns" {  } { { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns + Longest register pin " "Info: + Longest register to pin delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mfreq:inst3\|spk 1 REG LC4_C23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C23; Fanout = 2; REG Node = 'mfreq:inst3\|spk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { mfreq:inst3|spk } "NODE_NAME" } "" } } { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(4.800 ns) 5.600 ns spk 2 PIN PIN_41 0 " "Info: 2: + IC(0.800 ns) + CELL(4.800 ns) = 5.600 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'spk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.600 ns" { mfreq:inst3|spk spk } "NODE_NAME" } "" } } { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 136 520 696 152 "spk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.800 ns ( 85.71 % ) " "Info: Total cell delay = 4.800 ns ( 85.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns ( 14.29 % ) " "Info: Total interconnect delay = 0.800 ns ( 14.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.600 ns" { mfreq:inst3|spk spk } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.600 ns" { mfreq:inst3|spk spk } { 0.000ns 0.800ns } { 0.000ns 4.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "10.100 ns" { clk mfreq:inst3|fullspks mfreq:inst3|spk } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "10.100 ns" { clk clk~out mfreq:inst3|fullspks mfreq:inst3|spk } { 0.000ns 0.000ns 3.300ns 4.000ns } { 0.000ns 2.000ns 0.800ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.600 ns" { mfreq:inst3|spk spk } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.600 ns" { mfreq:inst3|spk spk } { 0.000ns 0.800ns } { 0.000ns 4.800ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "mfreq:inst3\|fullspks key\[7\] clk -4.900 ns register " "Info: th for register \"mfreq:inst3\|fullspks\" (data pin = \"key\[7\]\", clock pin = \"clk\") is -4.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_79 15 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 15; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { clk } "NODE_NAME" } "" } } { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 64 24 192 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 5.300 ns mfreq:inst3\|fullspks 2 REG LC1_C10 1 " "Info: 2: + IC(3.300 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C10; Fanout = 1; REG Node = 'mfreq:inst3\|fullspks'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "3.300 ns" { clk mfreq:inst3|fullspks } "NODE_NAME" } "" } } { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 37.74 % ) " "Info: Total cell delay = 2.000 ns ( 37.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 62.26 % ) " "Info: Total interconnect delay = 3.300 ns ( 62.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.300 ns" { clk mfreq:inst3|fullspks } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mfreq:inst3|fullspks } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 11.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 5.000 ns key\[7\] 1 PIN PIN_115 3 " "Info: 1: + IC(0.000 ns) + CELL(5.000 ns) = 5.000 ns; Loc. = PIN_115; Fanout = 3; PIN Node = 'key\[7\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "" { key[7] } "NODE_NAME" } "" } } { "example.bdf" "" { Schematic "D:/创新小组/quartus 2/example/example.bdf" { { 136 24 192 152 "key\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(2.400 ns) 8.900 ns keyncode:inst1\|spken~279 2 COMB LC8_C3 36 " "Info: 2: + IC(1.500 ns) + CELL(2.400 ns) = 8.900 ns; Loc. = LC8_C3; Fanout = 36; COMB Node = 'keyncode:inst1\|spken~279'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "3.900 ns" { key[7] keyncode:inst1|spken~279 } "NODE_NAME" } "" } } { "keyncode.vhd" "" { Text "D:/创新小组/quartus 2/example/keyncode.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.800 ns) 11.100 ns mfreq:inst3\|fullspks 3 REG LC1_C10 1 " "Info: 3: + IC(1.400 ns) + CELL(0.800 ns) = 11.100 ns; Loc. = LC1_C10; Fanout = 1; REG Node = 'mfreq:inst3\|fullspks'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "2.200 ns" { keyncode:inst1|spken~279 mfreq:inst3|fullspks } "NODE_NAME" } "" } } { "mfreq.vhd" "" { Text "D:/创新小组/quartus 2/example/mfreq.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.200 ns ( 73.87 % ) " "Info: Total cell delay = 8.200 ns ( 73.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 26.13 % ) " "Info: Total interconnect delay = 2.900 ns ( 26.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "11.100 ns" { key[7] keyncode:inst1|spken~279 mfreq:inst3|fullspks } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.100 ns" { key[7] key[7]~out keyncode:inst1|spken~279 mfreq:inst3|fullspks } { 0.000ns 0.000ns 1.500ns 1.400ns } { 0.000ns 5.000ns 2.400ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "5.300 ns" { clk mfreq:inst3|fullspks } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.300 ns" { clk clk~out mfreq:inst3|fullspks } { 0.000ns 0.000ns 3.300ns } { 0.000ns 2.000ns 0.000ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "example" "UNKNOWN" "V1" "D:/创新小组/quartus 2/example/db/example.quartus_db" { Floorplan "D:/创新小组/quartus 2/example/" "" "11.100 ns" { key[7] keyncode:inst1|spken~279 mfreq:inst3|fullspks } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "11.100 ns" { key[7] key[7]~out keyncode:inst1|spken~279 mfreq:inst3|fullspks } { 0.000ns 0.000ns 1.500ns 1.400ns } { 0.000ns 5.000ns 2.400ns 0.800ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}