📄 example.map.rpt
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; Total combinational functions ; 42 ;
; -- Total 4-input functions ; 24 ;
; -- Total 3-input functions ; 4 ;
; -- Total 2-input functions ; 13 ;
; -- Total 1-input functions ; 1 ;
; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 15 ;
; Total logic cells in carry chains ; 13 ;
; I/O pins ; 10 ;
; Maximum fan-out node ; keyncode:inst1|spken~279 ;
; Maximum fan-out ; 18 ;
; Total fan-out ; 171 ;
; Average fan-out ; 3.29 ;
+-----------------------------------+--------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------+
; |example ; 42 (8) ; 15 ; 0 ; 10 ; 27 (8) ; 0 (0) ; 15 (0) ; 13 (0) ; 0 (0) ; |example ;
; |keyncode:inst1| ; 13 (13) ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |example|keyncode:inst1 ;
; |mfreq:inst3| ; 21 (7) ; 15 ; 0 ; 0 ; 6 (5) ; 0 (0) ; 15 (2) ; 13 (0) ; 0 (0) ; |example|mfreq:inst3 ;
; |lpm_counter:count13_rtl_0| ; 14 (0) ; 13 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 13 (0) ; 13 (0) ; 0 (0) ; |example|mfreq:inst3|lpm_counter:count13_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 14 (14) ; 13 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 13 (13) ; 13 (13) ; 0 (0) ; |example|mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------+---+
; Latch Name ; ;
+-----------------------------------------------+---+
; keyncode:inst1|q[1] ; ;
; keyncode:inst1|q[0] ; ;
; keyncode:inst1|q[2] ; ;
; Number of user-specified and inferred latches ; 3 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 15 ;
; Number of registers using Synchronous Clear ; 13 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 14 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: mfreq:inst3|lpm_counter:count13_rtl_0 ;
+------------------------+-------------------+-------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+-------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 13 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; FLEX10KA ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/创新小组/quartus 2/example/example.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon Jul 17 09:22:44 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off example -c example
Info: Found 2 design units, including 1 entities, in source file keyncode.vhd
Info: Found design unit 1: keyncode-beha
Info: Found entity 1: keyncode
Info: Found 2 design units, including 1 entities, in source file mfreq.vhd
Info: Found design unit 1: mfreq-beha
Info: Found entity 1: mfreq
Info: Found 1 design units, including 1 entities, in source file example.bdf
Info: Found entity 1: example
Info: Elaborating entity "example" for the top level hierarchy
Info: Elaborating entity "mfreq" for hierarchy "mfreq:inst3"
Info: Elaborating entity "keyncode" for hierarchy "keyncode:inst1"
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=13) from the following logic: "mfreq:inst3|count13[0]~13"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Duplicate registers merged to single register
Info: Duplicate register "mfreq:inst3|count2" merged to single register "mfreq:inst3|spk"
Warning: Latch keyncode:inst1|q[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal key[5]
Warning: Latch keyncode:inst1|q[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal key[0]
Warning: Latch keyncode:inst1|q[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal key[0]
Info: Implemented 52 device resources after synthesis - the final resource count might be different
Info: Implemented 9 input pins
Info: Implemented 1 output pins
Info: Implemented 42 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
Info: Processing ended: Mon Jul 17 09:22:48 2006
Info: Elapsed time: 00:00:04
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