example.tan.rpt

这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来

; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPF10K10AQC208-3   ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                           ;
+-------+------------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                       ; To                                                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.17 MHz ( period = 16.900 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[5]  ; clk        ; clk      ; None                        ; None                      ; 14.400 ns               ;
; N/A   ; 59.88 MHz ( period = 16.700 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[0]  ; clk        ; clk      ; None                        ; None                      ; 14.200 ns               ;
; N/A   ; 59.88 MHz ( period = 16.700 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; clk        ; clk      ; None                        ; None                      ; 14.200 ns               ;
; N/A   ; 59.88 MHz ( period = 16.700 ns )               ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; mfreq:inst3|lpm_counter:count13_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; clk        ; clk      ; None                        ; None                      ; 14.200 ns               ;