lcd.map.rpt

用Verilog HDL 语言写的在LCD液晶上显示文字的源程序

; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_3ih ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_2 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 8           ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_4ih ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in J:/EH2000/598KT/verilogHDL/598KT-1K30/lcd/lcd.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Jul 15 09:39:42 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd
Warning: (10268) Verilog HDL information at lcd.v(114): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file lcd.v
    Info: Found entity 1: lcd
Info: Elaborating entity "lcd" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at lcd.v(20): object "ison" declared but not used
Warning: Verilog HDL unsupported feature warning at lcd.v(61): Initial Construct is not supported and will be ignored
Warning: Verilog HDL assignment warning at lcd.v(107): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at lcd.v(109): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(111): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(118): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(119): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(122): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(123): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(125): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(126): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(131): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(132): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(134): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(135): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(140): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(141): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(143): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at lcd.v(152): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(153): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(154): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(155): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(161): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(162): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(163): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(168): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(169): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(174): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(175): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(186): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(194): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at lcd.v(199): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(205): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(206): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(207): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(208): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(214): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(215): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(216): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(221): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(222): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(227): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(228): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(239): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(247): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at lcd.v(252): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(258): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(259): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(260): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(261): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(262): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(267): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(268): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(273): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(274): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(280): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(305): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(306): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(307): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(312): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(313): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(319): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(346): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(347): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(348): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(349): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(350): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(355): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(356): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(359): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(362): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(363): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(364): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(370): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(395): truncated value with size 32 to match size of target (7)
Warning: Verilog HDL assignment warning at lcd.v(396): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(397): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(402): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(403): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at lcd.v(409): truncated value with size 32 to match size of target (7)
Warning: Reduced register "rom1[0][6]" with stuck data_in port to stuck value GND
Warning: Reduced register "rom1[0][5]" with stuck data_in port to stuck value GND