lcd.fit.summary

用Verilog HDL 语言写的在LCD液晶上显示文字的源程序

Flow Status : Successful - Sat Jul 15 09:39:59 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : lcd
Top-level Entity Name : lcd
Family : ACEX1K
Device : EP1K30TC144-3
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 257 / 1,728 ( 14 % )
Total pins : 19 / 102 ( 18 % )
Total memory bits : 0 / 24,576 ( 0 % )
Total PLLs : 0