de2_tv.tan.summary

一个模拟视频输入转VGA视频输出的Verilog程序

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.159 ns
From           : TD_VS
To             : TV_to_VGA:u4|mACT_VS
From Clock     : 
To Clock       : OSC_27
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.956 ns
From           : I2C_AV_Config:u2|I2C_Controller:u0|SD_COUNTER[2]~reg0
To             : I2C_SCLK
From Clock     : OSC_50
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 6.187 ns
From           : OSC_27
To             : VGA_CLK
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.137 ns
From           : TD_VS
To             : TV_to_VGA:u4|itu_r656_decoder:U1|dul_port_c1024:CRR|I_a
From Clock     : 
To Clock       : TD_HS
Failed Paths   : 0

Type           : Clock Setup: 'OSC_27'
Slack          : 13.841 ns
Required Time  : 27.00 MHz ( period = 37.037 ns )
Actual Time    : 106.88 MHz ( period = 9.356 ns )
From           : TV_to_VGA:u4|itu_r656_decoder:U1|R3[4]
To             : TV_to_VGA:u4|itu_r656_decoder:U1|Field
From Clock     : OSC_27
To Clock       : OSC_27
Failed Paths   : 0

Type           : Clock Setup: 'VGA_Audio_PLL:u1|altpll:altpll_component|_clk1'
Slack          : 50.906 ns
Required Time  : 18.00 MHz ( period = 55.555 ns )
Actual Time    : 215.10 MHz ( period = 4.649 ns )
From           : AUDIO_DAC:u3|BCK_DIV[2]
To             : AUDIO_DAC:u3|oAUD_BCK
From Clock     : VGA_Audio_PLL:u1|altpll:altpll_component|_clk1
To Clock       : VGA_Audio_PLL:u1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'OSC_50'
Slack          : N/A
Required Time  : None
Actual Time    : 119.12 MHz ( period = 8.395 ns )
From           : LCD_TEST:u7|LUT_INDEX[3]
To             : LCD_TEST:u7|mLCD_ST.000001
From Clock     : OSC_50
To Clock       : OSC_50
Failed Paths   : 0

Type           : Clock Setup: 'TD_HS'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 180.57 MHz ( period = 5.538 ns )
From           : TV_to_VGA:u4|itu_r656_decoder:U1|dul_port_c1024:YYYR|RAM2:u|altsyncram:altsyncram_component|altsyncram_ktp1:auto_generated|ram_block1a0~porta_datain_reg0
To             : TV_to_VGA:u4|itu_r656_decoder:U1|dul_port_c1024:YYYR|RAM2:u|altsyncram:altsyncram_component|altsyncram_ktp1:auto_generated|ram_block1a0~porta_memory_reg0
From Clock     : TD_HS
To Clock       : TD_HS
Failed Paths   : 0

Type           : Clock Setup: 'TD_VS'
Slack          : N/A
Required Time  : None
Actual Time    : 199.36 MHz ( period = 5.016 ns )
From           : TV_to_VGA:u4|delay[4]
To             : TV_to_VGA:u4|sync_en
From Clock     : TD_VS
To Clock       : TD_VS
Failed Paths   : 0

Type           : Clock Hold: 'OSC_27'
Slack          : -2.888 ns
Required Time  : 27.00 MHz ( period = 37.037 ns )
Actual Time    : N/A
From           : TV_to_VGA:u4|itu_r656_decoder:U1|CCb[6]
To             : TV_to_VGA:u4|itu_r656_decoder:U1|dul_port_c1024:CBB|RAM2:u|altsyncram:altsyncram_component|altsyncram_ktp1:auto_generated|ram_block1a6~porta_datain_reg0
From Clock     : OSC_27
To Clock       : OSC_27
Failed Paths   : 98

Type           : Clock Hold: 'VGA_Audio_PLL:u1|altpll:altpll_component|_clk1'
Slack          : 0.610 ns
Required Time  : 18.00 MHz ( period = 55.555 ns )
Actual Time    : N/A
From           : AUDIO_DAC:u3|LRCK_1X
To             : AUDIO_DAC:u3|LRCK_1X
From Clock     : VGA_Audio_PLL:u1|altpll:altpll_component|_clk1
To Clock       : VGA_Audio_PLL:u1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Hold: 'TD_HS'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : TV_to_VGA:u4|itu_r656_decoder:U1|dul_port_c1024:CRR|I_a
To             : TV_to_VGA:u4|itu_r656_decoder:U1|dul_port_c1024:CRR|RAM2:u|altsyncram:altsyncram_component|altsyncram_ktp1:auto_generated|ram_block1a0~porta_we_reg
From Clock     : TD_HS
To Clock       : TD_HS
Failed Paths   : 130

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 228

--------------------------------------------------------------------------------------