de2_tv.fit.summary

一个模拟视频输入转VGA视频输出的Verilog程序

Flow Status : Successful - Wed Oct 05 16:03:48 2005
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : DE2_TV
Top-level Entity Name : DE2_TV
Family : Cyclone II
Device : EP2C35F672C8
Timing Models : Preliminary
Met timing requirements : N/A
Total logic elements : 1,264 / 33,216 ( 3 % )
Total registers : 627
Total pins : 423 / 475 ( 89 % )
Total virtual pins : 0
Total memory bits : 24,576 / 483,840 ( 5 % )
Embedded Multiplier 9-bit elements : 0 / 70 ( 0 % )
Total PLLs : 1 / 4 ( 25 % )