ftctrl.vhd

四位十进制频率计的顶层控制模块

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:22:06 06/22/2006 
-- Design Name: 
-- Module Name:    FTCTRL - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FTCTRL is
    Port ( CLKK : in  STD_LOGIC;
           CNT_EN : out  STD_LOGIC;
           RST_CNT : out  STD_LOGIC;
           Load : out  STD_LOGIC);
end FTCTRL;

architecture Behavioral of FTCTRL is
SIGNAL Div2CLK: STD_LOGIC:='0';
begin
PROCESS(CLKK)
BEGIN
	IF CLKK'EVENT AND CLKK='1' THEN
	Div2CLK <=NOT Div2CLK;
	END IF;
	END PROCESS;
	PROCESS(CLKK, Div2CLK)
	BEGIN
	IF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1';
	ELSE RST_CNT<='0';
	END IF;
	END PROCESS;
	Load <=NOT Div2CLK;
	CNT_EN<=Div2CLK;


end Behavioral;