wrlogo.vhd

通过UART从PC主机读取图片数据

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity wrlogo is
    Port (clk:in std_logic;
    		rst:in std_logic;
		RxAv:in std_logic;
		din:in std_logic_vector(7 downto 0);
		hloc:in std_logic_vector(9 downto 0);
		vloc:in std_logic_vector(9 downto 0);
		we:out std_logic;
		logo_flag:out std_logic;
		dout:out std_logic_vector(7 downto 0));
end wrlogo;

architecture Behavioral of wrlogo is
component logo is
	port (
	addr: IN std_logic_VECTOR(12 downto 0);
	clk: IN std_logic;
	din: IN std_logic_VECTOR(7 downto 0);
	dout: OUT std_logic_VECTOR(7 downto 0);
	we: IN std_logic);
end component;

signal webuf:std_logic;
signal readclk:std_logic;
signal ramclk:std_logic;
signal addr:std_logic_vector(12 downto 0);
signal doutbuf:std_logic_vector(7 downto 0);
signal mov_x,mov_y:std_logic_vector(9 downto 0);
signal inc_x,inc_y:std_logic_vector(9 downto 0);
begin
we<=webuf;

process(clk)
begin
  if clk'event and clk='1' then
    readclk<=not readclk;
  end if;
  if webuf='1' then
    ramclk<=RxAv;
  else
    ramclk<=readclk;
  end if;
end process;

process(ramclk,rst)
begin
  if rst='0' then
    webuf<='1';
    addr<="0000000000000";
  elsif ramclk'event and ramclk='1' then
    if webuf='1' then
	 if addr="1111111111111" then
	   addr<="0000000000000";
	   webuf<='0';
	 else
	   addr<=addr+1;
	   webuf<='1';
	 end if;
    elsif hloc>=mov_x and hloc<mov_x+128 and vloc>=mov_y and vloc<mov_y+64 then
      logo_flag<='1';
      dout<=doutbuf;
	 if addr="1111111111111" then
	   addr<="0000000000000";
	 else
	   addr<=addr+1;
	 end if;
    else
      logo_flag<='0';
      dout<="00000000";
    end if;
  end if;
end process;

process(rst,vloc(9))
begin
  if rst='0' then
    mov_x <= "0100000000";
    mov_y <= "0011100100";
    inc_x<="0000000001";
    inc_y<="0000000001";
  elsif vloc(9)'event and vloc(9)='1' then
      mov_x<=mov_x+inc_x;
      mov_y<=mov_y+inc_y;
	 if mov_x="0111111111" then
	   inc_x<="1111111111";
	 elsif mov_x<="0000000001" then
	   inc_x<="0000000001";
	 end if;
	 if mov_y>="0110011111" then
	   inc_y<="1111111111";
	 elsif mov_y="0000001111" then
	   inc_y<="0000000001";
	 end if;
  end if;
end process;

u0:logo port map
    (clk => ramclk,
     we => webuf,
	addr =>addr,
	din =>din,
	dout =>doutbuf);

end Behavioral;