coregen.log

来自「通过UART从PC主机读取图片数据」· LOG 代码 · 共 26 行

# Xilinx CORE Generator 6.2i
# User = lk
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in G:\doc\lab6\coregen.log
# lockprojectprops=false
# busformat=BusFormatAngleBracketNotRipped
# designflow=Vhdl
# expandedprojectpath=G:\doc\lab6
# expandedtaxonomy=/Memories_&_Storage_Elements
# flowvendor=Foundation_iSE
# formalverification=None
# selectedtaxonomy=/Memories_&_Storage_Elements/RAMs_&_ROMs
# simulationoutputproducts=Verilog VHDL
# taxonomymode=1
# xilinxfamily=Spartan2
# outputoption=DesignFlow
# overwritefiles=true
# simvendor=ModelSim
# expandedprojectpath=G:\doc\lab6
SETPROJECT .
Set current Project to G:\doc\lab6
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1313
XIPCPJSENDCORES virtex2