__projnav.log

通过UART从PC主机读取图片数据

    Found 1-bit register for signal <webuf>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 Accumulator(s).
	inferred  24 D-type flip-flop(s).
	inferred   3 Adder/Subtracter(s).
	inferred   6 Comparator(s).
Unit <wrlogo> synthesized.


Synthesizing Unit <uartrec>.
    Related source file is D:/vgashow/uartrec.vhd.
    Using one-hot encoding for signal <present_state>.
    Found 1-bit register for signal <rxav>.
    Found 8-bit register for signal <data>.
    Found 3-bit adder for signal <$n0021> created at line 59.
    Found 3-bit adder for signal <$n0025> created at line 77.
    Found 3-bit register for signal <bitpos>.
    Found 3-bit register for signal <cnt>.
    Found 8-bit register for signal <data_buf>.
    Found 7-bit up counter for signal <divcnt>.
    Found 3-bit register for signal <present_state>.
    Found 1-bit register for signal <recclk>.
    Summary:
	inferred   1 Counter(s).
	inferred  27 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <uartrec> synthesized.


Synthesizing Unit <top>.
    Related source file is D:/vgashow/top.vhd.
    Found 8 1-bit 2-to-1 multiplexers.
Unit <top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 26
  1-bit register                   : 16
  8-bit register                   : 3
  10-bit register                  : 2
  15-bit register                  : 1
  3-bit register                   : 3
  13-bit register                  : 1
# Counters                         : 3
  10-bit up counter                : 2
  7-bit up counter                 : 1
# Accumulators                     : 2
  10-bit up accumulator            : 2
# Multiplexers                     : 3
  2-to-1 multiplexer               : 3
# Adders/Subtractors               : 6
  15-bit addsub                    : 1
  3-bit adder                      : 3
  4-bit adder                      : 1
  13-bit adder                     : 1
# Comparators                      : 13
  11-bit comparator greatequal     : 3
  10-bit comparator less           : 2
  10-bit comparator lessequal      : 1
  11-bit comparator less           : 2
  11-bit comparator lessequal      : 2
  10-bit comparator greatequal     : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "ground.edn" "ground.ngo"
INFO:NgdBuild - Release 5.2.03i - edif2ngd F.31
INFO:NgdBuild - Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Writing the design to "ground.ngo"...
Loading core <ground> for timing and area information for instance <u0>.

Launcher: Executing edif2ngd -noa "logo.edn" "logo.ngo"
INFO:NgdBuild - Release 5.2.03i - edif2ngd F.31
INFO:NgdBuild - Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Writing the design to "logo.ngo"...
WARNING:Xst:1474 - Ports for core <logo> do not line up with declaration.  Core will not be loaded.

Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <top> ...

Optimizing unit <wrground> ...

Optimizing unit <vga> ...

Optimizing unit <uartrec> ...

Optimizing unit <wrlogo> ...
WARNING:Xst:1293 - FF/Latch  <inc_y_0> is constant in block <wrlogo>.
WARNING:Xst:1293 - FF/Latch  <inc_x_0> is constant in block <wrlogo>.

Mapping all equations...
Loading device for application Xst from file '2s300e.nph' in environment C:/Xilinx.
Building and optimizing final netlist ...
Register u1_inc_y_8 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_7 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_6 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_5 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_2 equivalent to u1_inc_y_1 has been removed
Register u1_inc_y_3 equivalent to u1_inc_y_1 has been removed
Register u1_inc_x_8 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_7 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_6 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_5 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_2 equivalent to u1_inc_x_1 has been removed
Register u1_inc_x_3 equivalent to u1_inc_x_1 has been removed
Register u1_inc_y_1 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_4 equivalent to u1_inc_y_9 has been removed
Register u1_inc_x_1 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_4 equivalent to u1_inc_x_9 has been removed
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 11.
WARNING:Xst:382 - Register BU589 is equivalent to BU63
WARNING:Xst:382 - Register BU592 is equivalent to BU66
WARNING:Xst:382 - Register BU595 is equivalent to BU69
WARNING:Xst:382 - Register BU598 is equivalent to BU72
WARNING:Xst:382 - Register BU601 is equivalent to BU75
WARNING:Xst:382 - Register BU589 is equivalent to BU63
WARNING:Xst:382 - Register BU592 is equivalent to BU66
WARNING:Xst:382 - Register BU595 is equivalent to BU69
WARNING:Xst:382 - Register BU598 is equivalent to BU72
WARNING:Xst:382 - Register BU601 is equivalent to BU75
FlipFlop u2_webuf has been replicated 1 time(s)
FlipFlop u2_addrbuf_0 has been replicated 1 time(s)
FlipFlop u2_addrbuf_2 has been replicated 1 time(s)
FlipFlop u2_addrbuf_1 has been replicated 1 time(s)
FlipFlop u2_addrbuf_3 has been replicated 1 time(s)
FlipFlop u2_addrbuf_4 has been replicated 1 time(s)
FlipFlop u2_addrbuf_5 has been replicated 1 time(s)
FlipFlop u2_addrbuf_7 has been replicated 1 time(s)
FlipFlop u2_addrbuf_6 has been replicated 1 time(s)
FlipFlop u2_addrbuf_8 has been replicated 1 time(s)
FlipFlop u2_addrbuf_9 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300efg456-6 

 Number of Slices:                     299  out of   3072     9%  
 Number of Slice Flip Flops:           147  out of   6144     2%  
 Number of 4 input LUTs:               526  out of   6144     8%  
 Number of bonded IOBs:                 12  out of    329     3%  
 Number of BRAMs:                       38  out of     16   237% (*) 
 Number of GCLKs:                        2  out of      4    50%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u0_recclk:q                        | NONE                   | 26    |
u4_vlocbuf_19:q                    | NONE                   | 22    |
u4_vgaclk:q                        | NONE                   | 10    |
u1_mmux_ramclk_result1:o           | NONE(*)(u1_dout_3)     | 23    |
u4_hs:o                            | NONE(*)(u4_vlocbuf_18) | 10    |
u2_mmux_sramclk_result1:o          | NONE(*)(u2_addrbuf_2_1)| 17    |
clk                                | BUFGP                  | 11    |
u2_mmux_sramclk_result1_1:o        | NONE(*)(u2_u0/b8)      | 48    |
u2_mmux_sramclk_result1_2:o        | NONE(*)(u2_addrbuf_8_1)| 18    |
-----------------------------------+------------------------+-------+
(*) These 5 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 10.524ns (Maximum Frequency: 95.021MHz)
   Minimum input arrival time before clock: 7.645ns
   Maximum output required time after clock: 12.718ns
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -quiet -dd d:\vgashow/_ngo -i -p xc2s300e-fg456-6 top.ngc
top.ngd 

Reading NGO file "D:/vgashow/top.ngc" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa "ground.edn" "d:\vgashow\_ngo\ground.ngo"
INFO:NgdBuild - Release 5.2.03i - edif2ngd F.31
INFO:NgdBuild - Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Writing the design to "d:/vgashow/_ngo/ground.ngo"...
Loading design module "d:\vgashow\_ngo\ground.ngo"...
Launcher: Executing edif2ngd -noa "logo.edn" "d:\vgashow\_ngo\logo.ngo"
INFO:NgdBuild - Release 5.2.03i - edif2ngd F.31
INFO:NgdBuild - Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Writing the design to "d:/vgashow/_ngo/logo.ngo"...
Loading design module "d:\vgashow\_ngo\logo.ngo"...
ERROR:NgdBuild:76 - File "d:\vgashow\_ngo\logo.ngo" cannot be merged into block
   "u1_u0" (TYPE="logo") because one or more pins on the block, including pin
   "addr<12>", were not found in the file.  Please make sure that all pins on
   the instantiated component match pins in the lower-level design block
   (irrespective of case).  If there are bussed pins on this block, make sure
   that the upper-level and lower-level netlists use the same bus-naming
   convention.

Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'u1_u0' with type 'logo' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   or the misspelling of a type name. Symbol 'logo' is not supported in target
   'spartan2e'.
WARNING:NgdBuild:477 - clock net 'u0_rxdin' has non-clock connections. These
   problematic connections include: pin i2 on block u0__n0010<2>7_g with type
   LUT4, pin i1 on block u0_ker93161 with type LUT3, pin i0 on block u0_ker93001
   with type LUT3, pin i3 on block u0__n0010<1>14 with type LUT4, pin I3 on
   block u0_ker9286_sw0 with type LUT4_D, pin I1 on block u0__n0019_sw0 with
   type LUT4_L, pin I2 on block u0_ker92071 with type LUT4_D
WARNING:NgdBuild:478 - clock net 'u0_rxdin' drives no clock pins

NGDBUILD Design Results Summary:
  Number of errors:     2
  Number of warnings:   2


One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "top.bld"...
ERROR: NGDBUILD failed
Reason: 

Completed process "Translate".


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Writing ground.jhd.

JHDPARSE complete -    0 errors,    0 warnings.


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    wrground.vhd
Scanning    wrground.vhd
Writing wrground.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/vgashow/uartrec.vhd in Library work.
Architecture behavioral of Entity uartrec is up to date.
Compiling vhdl file D:/vgashow/wrlogo.vhd in Library work.
Architecture behavioral of Entity wrlogo is up to date.
Compiling vhdl file D:/vgashow/wrground.vhd in Library work.
Entity <wrground> (Architecture <behavioral>) compiled.
Compiling vhdl file D:/vgashow/vga.vhd in Library work.
Architecture behavioral of Entity vga is up to date.
Compiling vhdl file D:/vgashow/top.vhd in Library work.
Architecture behavioral of Entity top is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <top> (Architecture <behavioral>).
WARNING:Xst:1541 - D:/vgashow/top.vhd line 94: Different binding for component: <wrground>. Port <din> does not match.
WARNING:Xst:819 - D:/vgashow/top.vhd line 112: The following signals are missing in the process sensitivity list:
   data_sram.
WARNING:Xst:819 - D:/vgashow/top.vhd line 121: The following signals are missing in the process sensitivity list:
   data_ram, data_srambuf.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <uartrec> (Architecture <behavioral>).
WARNING:Xst:766 - D:/vgashow/uartrec.vhd line 39: Generating a Black Box for component <ibuf>.
WARNING:Xst:766 - D:/vgashow/uartrec.vhd line 41: Generating a Black Box for component <bufg>.
Entity <uartrec> analyzed. Unit <uartrec> generated.

Analyzing Entity <wrlogo> (Architecture <behavioral>).
WARNING:Xst:819 - D:/vgashow/wrlogo.vhd line 43: The following signals are missing in the process sensitivity list:
   webuf, rxav, readclk.
WARNING:Xst:766 - D:/vgashow/wrlogo.vhd line 107: Generating a Black Box for component <logo>.
Entity <wrlogo> analyzed. Unit <wrlogo> generated.

Analyzing Entity <wrground> (Architecture <behavioral>).
WARNING:Xst:819 - D:/vgashow/wrground.vhd line 47: The following signals are missing in the process sensitivity list: