__projnav.log

通过UART从PC主机读取图片数据

Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    top.vhd
Scanning    top.vhd
Writing top.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    top.vhd
Scanning    top.vhd
Writing top.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    uartrec.vhd
Scanning    uartrec.vhd
Writing uartrec.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    uartrec.vhd
Scanning    uartrec.vhd
Writing uartrec.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    vga.vhd
Scanning    vga.vhd
Writing vga.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    vga.vhd
Scanning    vga.vhd
Writing vga.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    wrground.vhd
Scanning    wrground.vhd
Writing wrground.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    wrground.vhd
Scanning    wrground.vhd
Writing wrground.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    wrlogo.vhd
Scanning    wrlogo.vhd
Writing wrlogo.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    wrlogo.vhd
Scanning    wrlogo.vhd
Writing wrlogo.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Writing ground.jhd.

JHDPARSE complete -    0 errors,    0 warnings.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View Coregen Log".


Completed process "View Coregen Log".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Writing ground.jhd.

JHDPARSE complete -    0 errors,    0 warnings.


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    wrground.vhd
Scanning    wrground.vhd
Writing wrground.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Writing logo.jhd.

JHDPARSE complete -    0 errors,    0 warnings.


Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    wrlogo.vhd
Scanning    wrlogo.vhd
Writing wrlogo.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/vgashow/uartrec.vhd in Library work.
Entity <uartrec> (Architecture <behavioral>) compiled.
Compiling vhdl file D:/vgashow/wrlogo.vhd in Library work.
Entity <wrlogo> (Architecture <behavioral>) compiled.
Compiling vhdl file D:/vgashow/wrground.vhd in Library work.
Entity <wrground> (Architecture <behavioral>) compiled.
Compiling vhdl file D:/vgashow/vga.vhd in Library work.
Entity <vga> (Architecture <behavioral>) compiled.
Compiling vhdl file D:/vgashow/top.vhd in Library work.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <top> (Architecture <behavioral>).
WARNING:Xst:1541 - D:/vgashow/top.vhd line 94: Different binding for component: <wrground>. Port <din> does not match.
WARNING:Xst:819 - D:/vgashow/top.vhd line 112: The following signals are missing in the process sensitivity list:
   data_sram.
WARNING:Xst:819 - D:/vgashow/top.vhd line 121: The following signals are missing in the process sensitivity list:
   data_ram, data_srambuf.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <uartrec> (Architecture <behavioral>).
WARNING:Xst:766 - D:/vgashow/uartrec.vhd line 39: Generating a Black Box for component <ibuf>.
WARNING:Xst:766 - D:/vgashow/uartrec.vhd line 41: Generating a Black Box for component <bufg>.
Entity <uartrec> analyzed. Unit <uartrec> generated.

Analyzing Entity <wrlogo> (Architecture <behavioral>).
WARNING:Xst:819 - D:/vgashow/wrlogo.vhd line 43: The following signals are missing in the process sensitivity list:
   webuf, rxav, readclk.
WARNING:Xst:766 - D:/vgashow/wrlogo.vhd line 107: Generating a Black Box for component <logo>.
Entity <wrlogo> analyzed. Unit <wrlogo> generated.

Analyzing Entity <wrground> (Architecture <behavioral>).
WARNING:Xst:819 - D:/vgashow/wrground.vhd line 47: The following signals are missing in the process sensitivity list:
   rxav, readclk.
WARNING:Xst:766 - D:/vgashow/wrground.vhd line 98: Generating a Black Box for component <ground>.
Entity <wrground> analyzed. Unit <wrground> generated.

Analyzing Entity <vga> (Architecture <behavioral>).
WARNING:Xst:819 - D:/vgashow/vga.vhd line 47: The following signals are missing in the process sensitivity list:
   hs.
Entity <vga> analyzed. Unit <vga> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <vga>.
    Related source file is D:/vgashow/vga.vhd.
    Found 11-bit comparator greatequal for signal <$n0007> created at line 58.
    Found 11-bit comparator less for signal <$n0008> created at line 58.
    Found 11-bit comparator greatequal for signal <$n0009> created at line 63.
    Found 11-bit comparator less for signal <$n0010> created at line 63.
    Found 10-bit up counter for signal <hlocbuf>.
    Found 1-bit register for signal <vgaclk>.
    Found 10-bit up counter for signal <vlocbuf>.
    Summary:
	inferred   2 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   4 Comparator(s).
Unit <vga> synthesized.


Synthesizing Unit <wrground>.
    Related source file is D:/vgashow/wrground.vhd.
    Found 8-bit register for signal <dout>.
    Found 15-bit addsub for signal <$n0011>.
    Found 11-bit comparator greatequal for signal <$n0017> created at line 87.
    Found 11-bit comparator lessequal for signal <$n0018> created at line 69.
    Found 11-bit comparator lessequal for signal <$n0019> created at line 69.
    Found 15-bit register for signal <addrbuf>.
    Found 1-bit register for signal <readclk>.
    Found 1-bit register for signal <webuf>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  25 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <wrground> synthesized.


Synthesizing Unit <wrlogo>.
    Related source file is D:/vgashow/wrlogo.vhd.
    Found 8-bit register for signal <dout>.
    Found 1-bit register for signal <logo_flag>.
    Found 3-bit adder for signal <$n0014> created at line 67.
    Found 4-bit adder for signal <$n0015> created at line 67.
    Found 10-bit comparator greatequal for signal <$n0019> created at line 99.
    Found 13-bit adder for signal <$n0020> created at line 75.
    Found 10-bit comparator greatequal for signal <$n0021> created at line 67.
    Found 10-bit comparator less for signal <$n0022> created at line 67.
    Found 10-bit comparator greatequal for signal <$n0023> created at line 67.
    Found 10-bit comparator less for signal <$n0024> created at line 67.
    Found 10-bit comparator lessequal for signal <$n0025> created at line 95.
    Found 13-bit register for signal <addr>.
    Found 10-bit register for signal <inc_x>.
    Found 10-bit register for signal <inc_y>.
    Found 10-bit up accumulator for signal <mov_x>.
    Found 10-bit up accumulator for signal <mov_y>.
    Found 1-bit register for signal <readclk>.