vgashow.gfl

通过UART从PC主机读取图片数据

# VHDL : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/uartrec_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/uartrec_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/vga_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/vga_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/wrground_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/wrground_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/wrlogo_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/wrlogo_jhdparse_tcl.rsp
# Coregen : PDCL (jhdparse)
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.crp
coregen.prj
coregen.fin
# Coregen : View Coregen Log
ground.coregen_log
__projnav/xcoTOcoregen_log_tcl.rsp
# Regenerate Core
__projnav/xcoTO_regenCore_tcl.rsp
coregen.prj
__projnav/createCoregen.rsp
__projnav/xcoTO_regenCore_ground.rsp
# Coregen : PDCL (jhdparse)
# VHDL : PDCL (jhdparse)
__projnav/wrground_jhdparse_tcl.rsp
# Coregen : PDCL (jhdparse)
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.crp
coregen.prj
coregen.fin
# VHDL : PDCL (jhdparse)
__projnav/wrlogo_jhdparse_tcl.rsp
# xst flow : RunXST
top.syr
top.ngr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\vgashow/_ngo
top.ngd
top_ngdbuild.nav
top.bld
.untf
top.cmd_log
# Coregen : PDCL (jhdparse)
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# VHDL : PDCL (jhdparse)
__projnav/wrground_jhdparse_tcl.rsp
# xst flow : RunXST
top.syr
top.ngr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\vgashow/_ngo
top.ngd
top_ngdbuild.nav
top.bld
.untf
top.cmd_log
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# VHDL : PDCL (jhdparse)
__projnav/wrground_jhdparse_tcl.rsp
# xst flow : RunXST
top.syr
top.ngr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\vgashow/_ngo
top.ngd
top_ngdbuild.nav
top.bld
.untf
top.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/wrlogo_jhdparse_tcl.rsp
# xst flow : RunXST
top.syr
top.ngr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\vgashow/_ngo
top.ngd
top_ngdbuild.nav
top.bld
.untf
top.cmd_log
# Implementation : Map
top.nc1
top.mrp
top.pcf
top.ngm
top_map.ngm
top.mdf
top_map.ncd
__projnav/map.log
top.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top.dly
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.cmd_log
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Programming File Generation Report
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\vgashow/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top.ucf.untf
top.cmd_log
# Implementation : Map
top.nc1
top.mrp
top.pcf
top.ngm
top_map.ngm
top.mdf
top_map.ncd
__projnav/map.log
top.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top.dly
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.cmd_log
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Programming File Generation Report
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/wrlogo_jhdparse_tcl.rsp
# Coregen : PDCL (jhdparse)
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# VHDL : PDCL (jhdparse)
__projnav/wrlogo_jhdparse_tcl.rsp
# xst flow : RunXST
top.syr
top.ngr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\vgashow/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top.ucf.untf
top.cmd_log
# Implementation : Map
top.nc1
top.mrp
top.pcf
top.ngm
top_map.ngm
top.mdf
top_map.ncd
__projnav/map.log
top.cmd_log
# VHDL : PDCL (jhdparse)
__projnav/wrlogo_jhdparse_tcl.rsp
# Coregen : PDCL (jhdparse)
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# VHDL : PDCL (jhdparse)
__projnav/wrground_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/wrground_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/top_jhdparse_tcl.rsp
# xst flow : RunXST
top.syr
top.ngr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\vgashow/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top.ucf.untf
top.cmd_log
# Implementation : Map
top.nc1
top.mrp
top.pcf
top.ngm
top_map.ngm
top.mdf
top_map.ncd
__projnav/map.log
top.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top.dly
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.cmd_log
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Programming File Generation Report
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
d:\vgashow/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top.ucf.untf
top.cmd_log
# Implementation : Map
top.nc1
top.mrp
top.pcf
top.ngm
top_map.ngm
top.mdf
top_map.ncd
__projnav/map.log
top.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top.dly
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.cmd_log
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Programming File Generation Report
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Configure Device (iMPACT)
top.prm
top.isc
top.svf
xilinx.sys
top.mcs
top.exo
top.hex
top.tek
top.dst
top.dst_compressed
top.mpm
EndScriptMarker
0
# f2g Migration
_impact.cmd
_impact.log
top.ngr
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
top.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
c:\vga_new300\vgashow/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top.ucf.untf
top.cmd_log
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
__projnav/map.log
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Configure Device (iMPACT)
top.prm
top.isc
top.svf
xilinx.sys
top.mcs
top.exo
top.hex
top.tek
top.dst
top.dst_compressed
top.mpm
_impact.cmd
_impact.log
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Configure Device (iMPACT)
top.prm
top.isc
top.svf
xilinx.sys
top.mcs
top.exo
top.hex
top.tek
top.dst
top.dst_compressed
top.mpm
_impact.cmd
_impact.log
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
top.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
g:\doc\lab6/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top.ucf.untf
top.cmd_log
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
__projnav/map.log
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
top.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\fpga\exp6-vga/_ngo
top.ngd
top_ngdbuild.nav
top.bld
top.ucf.untf
top.cmd_log
# Implementation : Map
top_map.ncd
top.ngm
top.pcf
top.nc1
top.mrp
top_map.mrp
top.mdf
__projnav/map.log
top.cmd_log
MAP_NO_GUIDE_FILE_CPF "top"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
top.twr
top.twx
top.tsi
top.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
top.ncd
top.par
top.pad
top_pad.txt
top_pad.csv
top.pad_txt
top.dly
reportgen.log
top.xpi
top.grf
top.itr
top_last_par.ncd
__projnav/par.log
top.placed_ncd_tracker
top.routed_ncd_tracker
top.cmd_log
PAR_NO_GUIDE_FILE_CPF "top"
# Generate Programming File
__projnav/top_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
top.ut
# Generate Programming File
top.bgn
top.rbt
top.ll
top.msk
top.drc
top.nky
top.bit
top.bin
top.isc
top.cmd_log
# Configure Device (iMPACT)
top.prm
top.isc
top.svf
xilinx.sys
top.mcs
top.exo
top.hex
top.tek
top.dst
top.dst_compressed
top.mpm
_impact.cmd
_impact.log
# Configure Device (iMPACT)
top.prm
top.isc
top.svf
xilinx.sys
top.mcs
top.exo
top.hex
top.tek
top.dst
top.dst_compressed
top.mpm
_impact.cmd
_impact.log
# Generate PROM, ACE, or JTAG File
top.ace
xilinx.sys
top.mpm
top.mcs
top.prm
top.dst
top.exo
top.tek
top.hex
top.svf
top.stapl
impact.cmd
_impact.log
_impact.cmd
# Configure Device (iMPACT)
top.prm
top.isc
top.svf
xilinx.sys
top.mcs
top.exo
top.hex
top.tek
top.dst
top.dst_compressed
top.mpm
_impact.cmd
_impact.log
# Generate PROM, ACE, or JTAG File
top.ace
xilinx.sys
top.mpm
top.mcs
top.prm
top.dst
top.exo
top.tek
top.hex
top.svf
top.stapl
impact.cmd
_impact.log
_impact.cmd
# Configure Device (iMPACT)
top.prm
top.isc
top.svf
xilinx.sys
top.mcs
top.exo
top.hex
top.tek
top.dst
top.dst_compressed
top.mpm
_impact.cmd
_impact.log