coregen.crp
来自「通过UART从PC主机读取图片数据」· CRP 代码 · 共 8 行
CRP
8 行
SETPROJECT d:\vgashow
SET BusFormat = BusFormatAngleBracket
SET XilinxFamily = Spartan2
SET FlowVendor = Foundation_iSE
SET DesignFlow = Vhdl
SET SimulationOutputProducts = Verilog VHDL
SET LockProjectProps = false
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