top.par

通过UART从PC主机读取图片数据

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

CSU-3C87B3C11C6::  Fri Jun 23 11:35:24 2006


E:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd
top.pcf 


Constraints file: top.pcf

Loading device database for application Par from file "top_map.ncd".
   "top" is an NCD, version 2.38, device xc2v1000, package fg456, speed -4
Loading device for application Par from file '2v1000.nph' in environment
E:/Xilinx.
The STEPPING level for this design is 0.
Device speed data version:  PRODUCTION 1.117 2003-12-13.


Resolved that IOB <clk> must be placed at site AB12.
Resolved that IOB <rgb<0>> must be placed at site P3.
Resolved that IOB <rgb<1>> must be placed at site N4.
Resolved that IOB <rgb<2>> must be placed at site N3.
Resolved that IOB <rgb<3>> must be placed at site N5.
Resolved that IOB <hs> must be placed at site V3.
Resolved that IOB <rgb<4>> must be placed at site M3.
Resolved that IOB <rgb<5>> must be placed at site M4.
Resolved that IOB <rgb<6>> must be placed at site R1.
Resolved that IOB <rgb<7>> must be placed at site P2.
Resolved that IOB <vs> must be placed at site U4.
Resolved that IOB <rxd> must be placed at site AA10.
Resolved that IOB <rst> must be placed at site AB4.


Device utilization summary:

   Number of External IOBs            13 out of 324     4%
      Number of LOCed External IOBs   13 out of 13    100%

   Number of RAMB16s                  16 out of 40     40%
   Number of SLICEs                  123 out of 5120    2%

   Number of BUFGMUXs                  2 out of 16     12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9899f7) REAL time: 3 secs 

Phase 2.2
......
Phase 2.2 (Checksum:98aa13) REAL time: 3 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.8
.......................
Phase 5.8 (Checksum:9b93bb) REAL time: 3 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Phase 8.24
Phase 8.24 (Checksum:4c4b3f8) REAL time: 3 secs 

Phase 9.27
Phase 9.27 (Checksum:55d4a77) REAL time: 3 secs 

Writing design to file top.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 1149 unrouted;       REAL time: 4 secs 

Phase 2: 1005 unrouted;       REAL time: 6 secs 

Phase 3: 193 unrouted;       REAL time: 6 secs 

Phase 4: 0 unrouted;       REAL time: 7 secs 

Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       | BUFGMUX0P| No   |    7 |  0.055     |  1.135      |
+-------------------------+----------+------+------+------------+-------------+
|         u0_recclk       |   Local  |      |   21 |  0.183     |  1.705      |
+-------------------------+----------+------+------+------------+-------------+
|         u1_ramclk       |   Local  |      |   36 |  0.396     |  2.019      |
+-------------------------+----------+------+------+------------+-------------+
|     u4_vlocbuf<9>       |   Local  |      |   10 |  0.165     |  1.625      |
+-------------------------+----------+------+------+------------+-------------+
|    u4_vlocbuf_9_1       |   Local  |      |    7 |  0.099     |  1.608      |
+-------------------------+----------+------+------+------------+-------------+
|         u4_vgaclk       |   Local  |      |    7 |  0.008     |  1.575      |
+-------------------------+----------+------+------+------------+-------------+
|           hs_OBUF       |   Local  |      |    7 |  0.022     |  1.869      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 228


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.307
   The MAXIMUM PIN DELAY IS:                               6.269
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   4.846

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 7.00  d >= 7.00
   ---------   ---------   ---------   ---------   ---------   ---------
         645         216         146         114          28           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  88 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.