top.bld

通过UART从PC主机读取图片数据

Release 6.2i - ngdbuild G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -intstyle ise -dd e:\fpga\exp6-vga/_ngo -uc top.ucf -p
xc2v1000-fg456-4 top.ngc top.ngd 

Reading NGO file "E:/FPGA/Exp6-VGA/top.ngc" ...
Reading component libraries for design expansion...
Launcher: "logo.ngo" is up to date.
Loading design module "e:\fpga\exp6-vga\_ngo\logo.ngo"...

Annotating constraints to design from file "top.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'u0_rxdin' has non-clock connections. These
   problematic connections include:
     pin D on block u0_data_buf_7 with type FDE,
     pin D on block u0_data_buf_6 with type FDE,
     pin D on block u0_data_buf_0 with type FDE,
     pin D on block u0_data_buf_1 with type FDE,
     pin D on block u0_data_buf_2 with type FDE,
     pin D on block u0_data_buf_3 with type FDE,
     pin D on block u0_data_buf_4 with type FDE,
     pin D on block u0_data_buf_5 with type FDE,
     pin I1 on block u0_Ker518018 with type LUT2,
     pin I2 on block u0_present_state_FFd2-In28 with type LUT3,
     pin I2 on block u0_present_state_FFd3-In1 with type LUT4_D
WARNING:NgdBuild:478 - clock net 'u0_rxdin' drives no clock pins

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   2

Total memory usage is 42268 kilobytes

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...