top.mrp

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Release 6.2i Map G.28
Xilinx Mapping Report File for Design 'top'

Design Information
------------------
Command Line   : E:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2v1000-fg456-4 -cm
area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf 
Target Device  : x2v1000
Target Package : fg456
Target Speed   : -4
Mapper Version : virtex2 -- $Revision: 1.16.8.1 $
Mapped Date    : Fri Jun 23 11:35:21 2006

Design Summary
--------------
Number of errors:      0
Number of warnings:    4
Logic Utilization:
  Number of Slice Flip Flops:         101 out of  10,240    1%
  Number of 4 input LUTs:             166 out of  10,240    1%
Logic Distribution:
  Number of occupied Slices:          123 out of   5,120    2%
  Number of Slices containing only related logic:     123 out of     123  100%
  Number of Slices containing unrelated logic:          0 out of     123    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            196 out of  10,240    1%
  Number used as logic:               166
  Number used as a route-thru:         30

  Number of bonded IOBs:               13 out of     324    4%
    IOB Flip Flops:                     8
  Number of Block RAMs:                16 out of      40   40%
  Number of GCLKs:                      2 out of      16   12%

Total equivalent gate count for design:  1,050,912
Additional JTAG gate count for IOBs:  624
Peak Memory Usage:  84 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:MapLib:537 - The following Virtex Blockram(s) is/are being retargetted
   to Virtex2 Blockram(s). This will waste 75% of Virtex2 Blockram capacity. To
   obtain better utilization, Please re-run memory generator to retarget to
   Virtex2 Blockram modules:
   RAMB4_S1 symbol "u1_u0/B125" (output signal=u1_u0/N2155),
   RAMB4_S1 symbol "u1_u0/B128" (output signal=u1_u0/N2154),
   RAMB4_S1 symbol "u1_u0/B155" (output signal=u1_u0/N2658),
   RAMB4_S1 symbol "u1_u0/B158" (output signal=u1_u0/N2657),
   RAMB4_S1 symbol "u1_u0/B185" (output signal=u1_u0/N3161),
   RAMB4_S1 symbol "u1_u0/B188" (output signal=u1_u0/N3160),
   RAMB4_S1 symbol "u1_u0/B215" (output signal=u1_u0/N3664),
   RAMB4_S1 symbol "u1_u0/B218" (output signal=u1_u0/N3663),
   RAMB4_S1 symbol "u1_u0/B35" (output signal=u1_u0/N646),
   RAMB4_S1 symbol "u1_u0/B38" (output signal=u1_u0/N645),
   RAMB4_S1 symbol "u1_u0/B5" (output signal=u1_u0/N143),
   RAMB4_S1 symbol "u1_u0/B65" (output signal=u1_u0/N1149),
   RAMB4_S1 symbol "u1_u0/B68" (output signal=u1_u0/N1148),
   RAMB4_S1 symbol "u1_u0/B8" (output signal=u1_u0/N142),
   RAMB4_S1 symbol "u1_u0/B95" (output signal=u1_u0/N1652),
   RAMB4_S1 symbol "u1_u0/B98" (output signal=u1_u0/N1651)
WARNING:LIT:177 - Clock buffer BUFGMUX symbol "physical_group_u0_rxdin/u0_u1"
   (output signal=u0_rxdin) does not drive clock loads. Driving only non-clock
   loads with a clock buffer will cause ALL of the dedicated clock routing
   resources for this buffer to be wasted. Some of the non-clock loads are
   (maximum of 5 listed): 
   Pin D of u0_data_buf_7
   Pin D of u0_data_buf_6
   Pin D of u0_data_buf_0
   Pin D of u0_data_buf_1
   Pin D of u0_data_buf_2
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net u1_ramclk is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net hs_OBUF is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP),
   BUFG symbol "u0_u1" (output signal=u0_rxdin)

Section 4 - Removed Logic Summary
---------------------------------
   4 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC
GND 		u1_u0/GND
VCC 		u1_u0/VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| hs                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<0>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| rgb<1>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| rgb<2>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| rgb<3>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| rgb<4>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| rgb<5>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| rgb<6>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| rgb<7>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OFF1     |          |       |
| rst                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| rxd                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| vs                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 13
Number of Equivalent Gates for Design = 1,050,912
Number of RPM Macros = 0
Number of Hard Macros = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
PCILOGICs = 0
DCMs = 0
GCLKs = 2
ICAPs = 0
18X18 Multipliers = 0
Block RAMs = 16
TBUFs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 70
IOB Dual-Rate Flops not driven by LUTs = 0
IOB Dual-Rate Flops = 0
IOB Slave Pads = 0
IOB Master Pads = 0
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 0
IOB Flip Flops = 8
Unbonded IOBs = 0
Bonded IOBs = 13
Total Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MUXFs = 2
MULT_ANDs = 0
4 input LUTs used as Route-Thrus = 30
4 input LUTs = 166
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 70
Slice Flip Flops = 101
Slices = 123
Number of LUT signals with 4 loads = 2
Number of LUT signals with 3 loads = 2
Number of LUT signals with 2 loads = 38
Number of LUT signals with 1 load = 112
NGM Average fanout of LUT = 2.16
NGM Maximum fanout of LUT = 46
NGM Average fanin for LUT = 2.9819
Number of LUT symbols = 166
Number of IPAD symbols = 3
Number of IBUF symbols = 3