ground.edn

通过UART从PC主机读取图片数据

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2004 6 6 14 8 2)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 5.2.03i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2002 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_sinit_value = 0 ")
       (comment "c_has_en = 0 ")
       (comment "c_reg_inputs = 0 ")
       (comment "c_yclk_is_rising = 1 ")
       (comment "c_ysinit_is_high = 1 ")
       (comment "c_ywe_is_high = 1 ")
       (comment "c_yprimitive_type = 4kx1 ")
       (comment "c_ytop_addr = 1024 ")
       (comment "c_yhierarchy = hierarchy1 ")
       (comment "c_has_limit_data_pitch = 0 ")
       (comment "c_has_rdy = 0 ")
       (comment "c_write_mode = 0 ")
       (comment "c_width = 8 ")
       (comment "c_yuse_single_primitive = 0 ")
       (comment "c_has_nd = 0 ")
       (comment "c_has_we = 1 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_has_rfd = 0 ")
       (comment "c_has_din = 1 ")
       (comment "c_ybottom_addr = 0 ")
       (comment "c_pipe_stages = 0 ")
       (comment "c_yen_is_high = 1 ")
       (comment "c_family = virtex ")
       (comment "InstanceName = ground ")
       (comment "c_depth = 2 ")
       (comment "c_has_default_data = 1 ")
       (comment "c_limit_data_pitch = 8 ")
       (comment "c_has_sinit = 0 ")
       (comment "c_mem_init_file = mif_file_16_1 ")
       (comment "c_default_data = 0 ")
       (comment "c_ymake_bmm = 0 ")
       (comment "c_addr_width = 1 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell RAMB4_S8 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port WE (direction INPUT))
                   (port EN (direction INPUT))
                   (port RST (direction INPUT))
                   (port CLK (direction INPUT))
                   (port (rename DI_0_ "DI<0>") (direction INPUT))
                   (port (rename DI_1_ "DI<1>") (direction INPUT))
                   (port (rename DI_2_ "DI<2>") (direction INPUT))
                   (port (rename DI_3_ "DI<3>") (direction INPUT))
                   (port (rename DI_4_ "DI<4>") (direction INPUT))
                   (port (rename DI_5_ "DI<5>") (direction INPUT))
                   (port (rename DI_6_ "DI<6>") (direction INPUT))
                   (port (rename DI_7_ "DI<7>") (direction INPUT))
                   (port (rename DO_0_ "DO<0>") (direction OUTPUT))
                   (port (rename DO_1_ "DO<1>") (direction OUTPUT))
                   (port (rename DO_2_ "DO<2>") (direction OUTPUT))
                   (port (rename DO_3_ "DO<3>") (direction OUTPUT))
                   (port (rename DO_4_ "DO<4>") (direction OUTPUT))
                   (port (rename DO_5_ "DO<5>") (direction OUTPUT))
                   (port (rename DO_6_ "DO<6>") (direction OUTPUT))
                   (port (rename DO_7_ "DO<7>") (direction OUTPUT))
                   (port (rename ADDR_0_ "ADDR<0>") (direction INPUT))
                   (port (rename ADDR_1_ "ADDR<1>") (direction INPUT))
                   (port (rename ADDR_2_ "ADDR<2>") (direction INPUT))
                   (port (rename ADDR_3_ "ADDR<3>") (direction INPUT))
                   (port (rename ADDR_4_ "ADDR<4>") (direction INPUT))
                   (port (rename ADDR_5_ "ADDR<5>") (direction INPUT))
                   (port (rename ADDR_6_ "ADDR<6>") (direction INPUT))
                   (port (rename ADDR_7_ "ADDR<7>") (direction INPUT))
                   (port (rename ADDR_8_ "ADDR<8>") (direction INPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell ground
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename addr_0_ "addr<0>") (direction INPUT))
   (port ( rename clk "clk") (direction INPUT))
   (port ( rename din_7_ "din<7>") (direction INPUT))
   (port ( rename din_6_ "din<6>") (direction INPUT))
   (port ( rename din_5_ "din<5>") (direction INPUT))
   (port ( rename din_4_ "din<4>") (direction INPUT))
   (port ( rename din_3_ "din<3>") (direction INPUT))
   (port ( rename din_2_ "din<2>") (direction INPUT))
   (port ( rename din_1_ "din<1>") (direction INPUT))
   (port ( rename din_0_ "din<0>") (direction INPUT))
   (port ( rename we "we") (direction INPUT))
   (port ( rename dout_7_ "dout<7>") (direction OUTPUT))
   (port ( rename dout_6_ "dout<6>") (direction OUTPUT))
   (port ( rename dout_5_ "dout<5>") (direction OUTPUT))
   (port ( rename dout_4_ "dout<4>") (direction OUTPUT))
   (port ( rename dout_3_ "dout<3>") (direction OUTPUT))
   (port ( rename dout_2_ "dout<2>") (direction OUTPUT))
   (port ( rename dout_1_ "dout<1>") (direction OUTPUT))
   (port ( rename dout_0_ "dout<0>") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance B5
      (viewRef view_1 (cellRef RAMB4_S8 (libraryRef xilinxun)))
      (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000"))
   )
   (net N0
    (joined
      (portRef G (instanceRef GND))
      (portRef RST (instanceRef B5))
      (portRef ADDR_1_ (instanceRef B5))
      (portRef ADDR_2_ (instanceRef B5))
      (portRef ADDR_3_ (instanceRef B5))
      (portRef ADDR_4_ (instanceRef B5))
      (portRef ADDR_5_ (instanceRef B5))
      (portRef ADDR_6_ (instanceRef B5))
      (portRef ADDR_7_ (instanceRef B5))
      (portRef ADDR_8_ (instanceRef B5))
    )
   )
   (net N1
    (joined
      (portRef P (instanceRef VCC))
      (portRef EN (instanceRef B5))
    )
   )
   (net (rename N59 "addr<0>")
    (joined
      (portRef addr_0_)
      (portRef ADDR_0_ (instanceRef B5))
    )
   )
   (net (rename N60 "clk")
    (joined
      (portRef clk)
      (portRef CLK (instanceRef B5))
    )
   )
   (net (rename N61 "din<7>")
    (joined
      (portRef din_7_)
      (portRef DI_7_ (instanceRef B5))
    )
   )
   (net (rename N62 "din<6>")
    (joined
      (portRef din_6_)
      (portRef DI_6_ (instanceRef B5))
    )
   )
   (net (rename N63 "din<5>")
    (joined
      (portRef din_5_)
      (portRef DI_5_ (instanceRef B5))
    )
   )
   (net (rename N64 "din<4>")
    (joined
      (portRef din_4_)
      (portRef DI_4_ (instanceRef B5))
    )
   )
   (net (rename N65 "din<3>")
    (joined
      (portRef din_3_)
      (portRef DI_3_ (instanceRef B5))
    )
   )
   (net (rename N66 "din<2>")
    (joined
      (portRef din_2_)
      (portRef DI_2_ (instanceRef B5))
    )
   )
   (net (rename N67 "din<1>")
    (joined
      (portRef din_1_)
      (portRef DI_1_ (instanceRef B5))
    )
   )
   (net (rename N68 "din<0>")
    (joined
      (portRef din_0_)
      (portRef DI_0_ (instanceRef B5))
    )
   )
   (net (rename N69 "dout<7>")
    (joined
      (portRef dout_7_)
      (portRef DO_7_ (instanceRef B5))
    )
   )
   (net (rename N70 "dout<6>")
    (joined
      (portRef dout_6_)
      (portRef DO_6_ (instanceRef B5))
    )
   )
   (net (rename N71 "dout<5>")
    (joined
      (portRef dout_5_)
      (portRef DO_5_ (instanceRef B5))
    )
   )
   (net (rename N72 "dout<4>")
    (joined
      (portRef dout_4_)
      (portRef DO_4_ (instanceRef B5))
    )
   )
   (net (rename N73 "dout<3>")
    (joined
      (portRef dout_3_)
      (portRef DO_3_ (instanceRef B5))
    )
   )
   (net (rename N74 "dout<2>")
    (joined
      (portRef dout_2_)
      (portRef DO_2_ (instanceRef B5))
    )
   )
   (net (rename N75 "dout<1>")
    (joined
      (portRef dout_1_)
      (portRef DO_1_ (instanceRef B5))
    )
   )
   (net (rename N76 "dout<0>")
    (joined
      (portRef dout_0_)
      (portRef DO_0_ (instanceRef B5))
    )
   )
   (net (rename N82 "we")
    (joined
      (portRef we)
      (portRef WE (instanceRef B5))
    )
   )
))))
(design ground (cellRef ground (libraryRef test_lib))
  (property PART (string "XCV100BG256") (owner "Xilinx")))
)