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通过UART从PC主机读取图片数据

     MUXCY:CI->O           1   0.053   0.000  u4_vlocbuf_inst_cy_12 (u4_vlocbuf_inst_cy_12)
     MUXCY:CI->O           1   0.053   0.000  u4_vlocbuf_inst_cy_13 (u4_vlocbuf_inst_cy_13)
     MUXCY:CI->O           1   0.053   0.000  u4_vlocbuf_inst_cy_14 (u4_vlocbuf_inst_cy_14)
     MUXCY:CI->O           1   0.053   0.000  u4_vlocbuf_inst_cy_15 (u4_vlocbuf_inst_cy_15)
     MUXCY:CI->O           0   0.053   0.000  u4_vlocbuf_inst_cy_16 (u4_vlocbuf_inst_cy_16)
     XORCY:CI->O           2   1.274   0.000  u4_vlocbuf_inst_sum_16 (u4_vlocbuf_inst_sum_16)
     FDCPE:D                   0.370          u4_vlocbuf_9
    ----------------------------------------
    Total                      5.567ns (3.865ns logic, 1.702ns route)
                                       (69.4% logic, 30.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u0_recclk:Q'
Delay:               4.504ns (Levels of Logic = 3)
  Source:            u0_present_state_FFd3 (FF)
  Destination:       u0_cnt_1 (FF)
  Source Clock:      u0_recclk:Q rising
  Destination Clock: u0_recclk:Q rising

  Data Path: u0_present_state_FFd3 to u0_cnt_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.568   0.747  u0_present_state_FFd3 (u0_present_state_FFd3)
     LUT2:I0->O            1   0.439   0.517  u0_Ker518018 (CHOICE606)
     MUXF5:S->O            3   0.699   0.724  u0_Ker518025 (u0_N5182)
     LUT4_L:I3->LO         1   0.439   0.000  u0__n0015<1>1 (u0__n0015<1>)
     FD:D                      0.370          u0_cnt_1
    ----------------------------------------
    Total                      4.504ns (2.515ns logic, 1.989ns route)
                                       (55.8% logic, 44.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u4_vgaclk:Q'
Delay:               5.452ns (Levels of Logic = 13)
  Source:            u4_hlocbuf_6 (FF)
  Destination:       u4_hlocbuf_9 (FF)
  Source Clock:      u4_vgaclk:Q rising
  Destination Clock: u4_vgaclk:Q rising

  Data Path: u4_hlocbuf_6 to u4_hlocbuf_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   0.568   0.771  u4_hlocbuf_6 (u4_hlocbuf_6)
     LUT4:I0->O            7   0.439   0.816  u4__n00038 (CHOICE719)
     LUT4_D:I0->LO         1   0.439   0.000  u4__n000325 (N12930)
     MUXCY:S->O            1   0.298   0.000  u4_hlocbuf_inst_cy_7 (u4_hlocbuf_inst_cy_7)
     MUXCY:CI->O           1   0.053   0.000  u4_hlocbuf_inst_cy_8 (u4_hlocbuf_inst_cy_8)
     MUXCY:CI->O           1   0.053   0.000  u4_hlocbuf_inst_cy_9 (u4_hlocbuf_inst_cy_9)
     MUXCY:CI->O           1   0.053   0.000  u4_hlocbuf_inst_cy_10 (u4_hlocbuf_inst_cy_10)
     MUXCY:CI->O           1   0.053   0.000  u4_hlocbuf_inst_cy_11 (u4_hlocbuf_inst_cy_11)
     MUXCY:CI->O           1   0.053   0.000  u4_hlocbuf_inst_cy_12 (u4_hlocbuf_inst_cy_12)
     MUXCY:CI->O           1   0.053   0.000  u4_hlocbuf_inst_cy_13 (u4_hlocbuf_inst_cy_13)
     MUXCY:CI->O           1   0.053   0.000  u4_hlocbuf_inst_cy_14 (u4_hlocbuf_inst_cy_14)
     MUXCY:CI->O           1   0.053   0.000  u4_hlocbuf_inst_cy_15 (u4_hlocbuf_inst_cy_15)
     MUXCY:CI->O           0   0.053   0.000  u4_hlocbuf_inst_cy_16 (u4_hlocbuf_inst_cy_16)
     XORCY:CI->O           1   1.274   0.000  u4_hlocbuf_inst_sum_16 (u4_hlocbuf_inst_sum_16)
     FDCPE:D                   0.370          u4_hlocbuf_9
    ----------------------------------------
    Total                      5.452ns (3.865ns logic, 1.587ns route)
                                       (70.9% logic, 29.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u1_Mmux_ramclk_Result1:O'
Delay:               5.523ns (Levels of Logic = 15)
  Source:            u1_addr_0 (FF)
  Destination:       u1_addr_12 (FF)
  Source Clock:      u1_Mmux_ramclk_Result1:O rising
  Destination Clock: u1_Mmux_ramclk_Result1:O rising

  Data Path: u1_addr_0 to u1_addr_12
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            19   0.568   1.035  u1_addr_0 (u1_addr_0)
     LUT1_L:I0->LO         1   0.439   0.000  u1_Madd__n0024_inst_lut2_371 (u1_Madd__n0024_inst_lut2_37)
     MUXCY:S->O            1   0.298   0.000  u1_Madd__n0024_inst_cy_47 (u1_Madd__n0024_inst_cy_47)
     MUXCY:CI->O           1   0.053   0.000  u1_Madd__n0024_inst_cy_48 (u1_Madd__n0024_inst_cy_48)
     MUXCY:CI->O           1   0.053   0.000  u1_Madd__n0024_inst_cy_49 (u1_Madd__n0024_inst_cy_49)
     MUXCY:CI->O           1   0.053   0.000  u1_Madd__n0024_inst_cy_50 (u1_Madd__n0024_inst_cy_50)
     MUXCY:CI->O           1   0.053   0.000  u1_Madd__n0024_inst_cy_51 (u1_Madd__n0024_inst_cy_51)
     MUXCY:CI->O           1   0.053   0.000  u1_Madd__n0024_inst_cy_52 (u1_Madd__n0024_inst_cy_52)
     MUXCY:CI->O           1   0.053   0.000  u1_Madd__n0024_inst_cy_53 (u1_Madd__n0024_inst_cy_53)
     MUXCY:CI->O           1   0.053   0.000  u1_Madd__n0024_inst_cy_54 (u1_Madd__n0024_inst_cy_54)
     MUXCY:CI->O           1   0.053   0.000  u1_Madd__n0024_inst_cy_55 (u1_Madd__n0024_inst_cy_55)
     MUXCY:CI->O           1   0.053   0.000  u1_Madd__n0024_inst_cy_56 (u1_Madd__n0024_inst_cy_56)
     MUXCY:CI->O           1   0.053   0.000  u1_Madd__n0024_inst_cy_57 (u1_Madd__n0024_inst_cy_57)
     MUXCY:CI->O           0   0.053   0.000  u1_Madd__n0024_inst_cy_58 (u1_Madd__n0024_inst_cy_58)
     XORCY:CI->O           1   1.274   0.517  u1_Madd__n0024_inst_sum_39 (u1__n0024<12>)
     LUT4_L:I0->LO         1   0.439   0.000  u1__n0000<12>1 (u1__n0000<12>)
     FDCE:D                    0.370          u1_addr_12
    ----------------------------------------
    Total                      5.523ns (3.971ns logic, 1.552ns route)
                                       (71.9% logic, 28.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u4_vlocbuf_9:Q'
Delay:               4.076ns (Levels of Logic = 8)
  Source:            u1_inc_x_9 (FF)
  Destination:       u1_mov_x_7 (FF)
  Source Clock:      u4_vlocbuf_9:Q rising
  Destination Clock: u4_vlocbuf_9:Q rising

  Data Path: u1_inc_x_9 to u1_mov_x_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   0.568   0.862  u1_inc_x_9 (u1_inc_x_9)
     LUT2_L:I0->LO         1   0.439   0.000  u1_mov_x_Madd__n0000_inst_lut2_81 (u1_mov_x_Madd__n0000_inst_lut2_8)
     MUXCY:S->O            1   0.298   0.000  u1_mov_x_Madd__n0000_inst_cy_19 (u1_mov_x_Madd__n0000_inst_cy_19)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_x_Madd__n0000_inst_cy_20 (u1_mov_x_Madd__n0000_inst_cy_20)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_x_Madd__n0000_inst_cy_21 (u1_mov_x_Madd__n0000_inst_cy_21)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_x_Madd__n0000_inst_cy_22 (u1_mov_x_Madd__n0000_inst_cy_22)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_x_Madd__n0000_inst_cy_23 (u1_mov_x_Madd__n0000_inst_cy_23)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_x_Madd__n0000_inst_cy_24 (u1_mov_x_Madd__n0000_inst_cy_24)
     XORCY:CI->O           1   1.274   0.000  u1_mov_x_Madd__n0000_inst_sum_24 (u1_mov_x__n0000<7>)
     FDC:D                     0.370          u1_mov_x_7
    ----------------------------------------
    Total                      4.076ns (3.214ns logic, 0.862ns route)
                                       (78.8% logic, 21.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u4_vlocbuf_9_1:Q'
Delay:               4.120ns (Levels of Logic = 11)
  Source:            u1_mov_y_0 (FF)
  Destination:       u1_mov_y_9 (FF)
  Source Clock:      u4_vlocbuf_9_1:Q rising
  Destination Clock: u4_vlocbuf_9_1:Q rising

  Data Path: u1_mov_y_0 to u1_mov_y_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              4   0.568   0.747  u1_mov_y_0 (u1_mov_y_0)
     LUT1_L:I0->LO         2   0.439   0.000  u1_mov_y_Madd__n0000_inst_lut2_711 (u1_mov_y_Madd__n0000_inst_lut2_7)
     MUXCY:S->O            1   0.298   0.000  u1_mov_y_Madd__n0000_inst_cy_18 (u1_mov_y_Madd__n0000_inst_cy_18)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_y_Madd__n0000_inst_cy_19 (u1_mov_y_Madd__n0000_inst_cy_19)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_y_Madd__n0000_inst_cy_20 (u1_mov_y_Madd__n0000_inst_cy_20)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_y_Madd__n0000_inst_cy_21 (u1_mov_y_Madd__n0000_inst_cy_21)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_y_Madd__n0000_inst_cy_22 (u1_mov_y_Madd__n0000_inst_cy_22)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_y_Madd__n0000_inst_cy_23 (u1_mov_y_Madd__n0000_inst_cy_23)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_y_Madd__n0000_inst_cy_24 (u1_mov_y_Madd__n0000_inst_cy_24)
     MUXCY:CI->O           1   0.053   0.000  u1_mov_y_Madd__n0000_inst_cy_25 (u1_mov_y_Madd__n0000_inst_cy_25)
     MUXCY:CI->O           0   0.053   0.000  u1_mov_y_Madd__n0000_inst_cy_26 (u1_mov_y_Madd__n0000_inst_cy_26)
     XORCY:CI->O           1   1.274   0.000  u1_mov_y_Madd__n0000_inst_sum_26 (u1_mov_y__n0000<9>)
     FDC:D                     0.370          u1_mov_y_9
    ----------------------------------------
    Total                      4.120ns (3.373ns logic, 0.747ns route)
                                       (81.9% logic, 18.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u0_recclk:Q'
Offset:              6.029ns (Levels of Logic = 5)
  Source:            rxd (PAD)
  Destination:       u0_cnt_1 (FF)
  Destination Clock: u0_recclk:Q rising

  Data Path: rxd to u0_cnt_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.825   0.517  u0_u0 (u0_rxdbuf)
     BUFG:I->O            11   0.589   0.909  u0_u1 (u0_rxdin)
     LUT2:I1->O            1   0.439   0.517  u0_Ker518018 (CHOICE606)
     MUXF5:S->O            3   0.699   0.724  u0_Ker518025 (u0_N5182)
     LUT4_L:I3->LO         1   0.439   0.000  u0__n0015<1>1 (u0__n0015<1>)
     FD:D                      0.370          u0_cnt_1
    ----------------------------------------
    Total                      6.029ns (3.361ns logic, 2.668ns route)
                                       (55.7% logic, 44.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u1_Mmux_ramclk_Result1:O'
Offset:              3.045ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       u1_dout_7 (FF)
  Destination Clock: u1_Mmux_ramclk_Result1:O rising

  Data Path: rst to u1_dout_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.825   0.702  rst_IBUF (rst_IBUF)
     LUT2:I0->O            8   0.439   0.839  u1__n00091 (u1__n0009)
     FDE:CE                    0.240          u1_dout_1
    ----------------------------------------
    Total                      3.045ns (1.504ns logic, 1.541ns route)
                                       (49.4% logic, 50.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u4_vgaclk:Q'
Offset:              8.027ns (Levels of Logic = 3)
  Source:            u4_hlocbuf_8 (FF)
  Destination:       hs (PAD)
  Source Clock:      u4_vgaclk:Q rising

  Data Path: u4_hlocbuf_8 to hs
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            5   0.568   0.771  u4_hlocbuf_8 (u4_hlocbuf_8)
     LUT3:I0->O            1   0.439   0.517  u4_hs_SW0 (N11657)
     LUT4:I0->O           12   0.439   0.931  u4_hs (hs_OBUF)
     OBUF:I->O                 4.361          hs_OBUF (hs)
    ----------------------------------------
    Total                      8.027ns (5.807ns logic, 2.220ns route)
                                       (72.3% logic, 27.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u4_hs:O'
Offset:              8.592ns (Levels of Logic = 4)
  Source:            u4_vlocbuf_2 (FF)
  Destination:       vs (PAD)
  Source Clock:      u4_hs:O rising

  Data Path: u4_vlocbuf_2 to vs
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            6   0.568   0.793  u4_vlocbuf_2 (u4_vlocbuf_2)
     LUT3:I0->O            1   0.439   0.517  u4_vs37_SW1 (N12902)
     LUT4:I3->O            1   0.439   0.517  u4_vs37 (CHOICE585)
     LUT2:I1->O            1   0.439   0.517  u4_vs48 (vs_OBUF)
     OBUF:I->O                 4.361          vs_OBUF (vs)
    ----------------------------------------
    Total                      8.592ns (6.246ns logic, 2.346ns route)
                                       (72.7% logic, 27.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u1_Mmux_ramclk_Result1:O'
Offset:              5.446ns (Levels of Logic = 1)
  Source:            u1_dout_7 (FF)
  Destination:       rgb<7> (PAD)
  Source Clock:      u1_Mmux_ramclk_Result1:O rising

  Data Path: u1_dout_7 to rgb<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.568   0.517  u1_dout_7 (u1_dout_7)
     OBUF:I->O                 4.361          rgb_7_OBUF (rgb<7>)
    ----------------------------------------
    Total                      5.446ns (4.929ns logic, 0.517ns route)
                                       (90.5% logic, 9.5% route)

=========================================================================
CPU : 16.64 / 18.08 s | Elapsed : 17.00 / 18.00 s
 
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Total memory usage is 81896 kilobytes