top.syr

通过UART从PC主机读取图片数据

 7-bit up counter                  : 1
# Accumulators                     : 2
 10-bit up accumulator             : 2
# Registers                        : 24
 3-bit register                    : 2
 1-bit register                    : 17
 8-bit register                    : 2
 13-bit register                   : 1
 10-bit register                   : 2
# Comparators                      : 10
 10-bit comparator lessequal       : 1
 10-bit comparator less            : 2
 10-bit comparator greatequal      : 3
 11-bit comparator less            : 2
 11-bit comparator greatequal      : 2
# Multiplexers                     : 2
 8-bit 2-to-1 multiplexer          : 1
 1-bit 2-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "logo.ngo" is up to date.
Loading core <logo> for timing and area information for instance <u0>.
WARNING:Xst:1291 - FF/Latch <logo_flag> is unconnected in block <u1>.

Optimizing unit <top> ...

Optimizing unit <vga> ...

Optimizing unit <uartrec> ...

Optimizing unit <wrlogo> ...
WARNING:Xst:1710 - FF/Latch  <inc_y_0> (without init value) is constant in block <wrlogo>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <inc_x_0> (without init value) is constant in block <wrlogo>.
Loading device for application Xst from file '2v1000.nph' in environment E:/Xilinx.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <u1_logo_flag> is unconnected in block <top>.
Building and optimizing final netlist ...
Register u1_inc_y_1 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_3 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_4 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_5 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_6 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_7 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_8 equivalent to u1_inc_y_9 has been removed
Register u1_inc_y_2 equivalent to u1_inc_y_9 has been removed
Register u1_inc_x_1 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_3 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_4 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_5 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_6 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_7 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_8 equivalent to u1_inc_x_9 has been removed
Register u1_inc_x_2 equivalent to u1_inc_x_9 has been removed
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 2.
WARNING:Xst:382 - Register BU42 is equivalent to BU12
WARNING:Xst:382 - Register BU72 is equivalent to BU12
WARNING:Xst:382 - Register BU102 is equivalent to BU12
WARNING:Xst:382 - Register BU132 is equivalent to BU12
WARNING:Xst:382 - Register BU162 is equivalent to BU12
WARNING:Xst:382 - Register BU192 is equivalent to BU12
WARNING:Xst:382 - Register BU222 is equivalent to BU12
WARNING:Xst:382 - Register BU72 is equivalent to BU42
WARNING:Xst:382 - Register BU102 is equivalent to BU42
WARNING:Xst:382 - Register BU132 is equivalent to BU42
WARNING:Xst:382 - Register BU162 is equivalent to BU42
WARNING:Xst:382 - Register BU192 is equivalent to BU42
WARNING:Xst:382 - Register BU222 is equivalent to BU42
WARNING:Xst:382 - Register BU102 is equivalent to BU72
WARNING:Xst:382 - Register BU132 is equivalent to BU72
WARNING:Xst:382 - Register BU162 is equivalent to BU72
WARNING:Xst:382 - Register BU192 is equivalent to BU72
WARNING:Xst:382 - Register BU222 is equivalent to BU72
WARNING:Xst:382 - Register BU132 is equivalent to BU102
WARNING:Xst:382 - Register BU162 is equivalent to BU102
WARNING:Xst:382 - Register BU192 is equivalent to BU102
WARNING:Xst:382 - Register BU222 is equivalent to BU102
WARNING:Xst:382 - Register BU162 is equivalent to BU132
WARNING:Xst:382 - Register BU192 is equivalent to BU132
WARNING:Xst:382 - Register BU222 is equivalent to BU132
WARNING:Xst:382 - Register BU192 is equivalent to BU162
WARNING:Xst:382 - Register BU222 is equivalent to BU162
WARNING:Xst:382 - Register BU222 is equivalent to BU192
FlipFlop u4_vlocbuf_9 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 13

Macro Statistics :
# Registers                        : 60
#      1-bit register              : 54
#      13-bit register             : 1
#      3-bit register              : 2
#      7-bit register              : 1
#      8-bit register              : 2
# Counters                         : 2
#      10-bit up counter           : 2
# Multiplexers                     : 2
#      2-to-1 multiplexer          : 2
# Adders/Subtractors               : 4
#      10-bit adder                : 2
#      13-bit adder                : 1
#      7-bit adder                 : 1
# Comparators                      : 10
#      10-bit comparator greatequal: 3
#      10-bit comparator less      : 2
#      10-bit comparator lessequal : 1
#      11-bit comparator greatequal: 2
#      11-bit comparator less      : 2

Cell Usage :
# BELS                             : 368
#      GND                         : 2
#      LUT1                        : 10
#      LUT1_L                      : 16
#      LUT2                        : 54
#      LUT2_L                      : 20
#      LUT3                        : 10
#      LUT3_D                      : 1
#      LUT3_L                      : 6
#      LUT4                        : 60
#      LUT4_D                      : 6
#      LUT4_L                      : 27
#      MUXCY                       : 96
#      MUXF5                       : 2
#      VCC                         : 2
#      XORCY                       : 56
# FlipFlops/Latches                : 109
#      FD                          : 7
#      FDC                         : 15
#      FDCE                        : 15
#      FDCPE                       : 21
#      FDE                         : 32
#      FDP                         : 5
#      FDPE                        : 1
#      FDR                         : 10
#      FDS                         : 3
# RAMS                             : 16
#      RAMB4_S1                    : 16
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 2
#      OBUF                        : 10
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v1000fg456-4 

 Number of Slices:                     120  out of   5120     2%  
 Number of Slice Flip Flops:           109  out of  10240     1%  
 Number of 4 input LUTs:               210  out of  10240     2%  
 Number of bonded IOBs:                 12  out of    324     3%  
 Number of BRAMs:                       16  out of     40    40%  
 Number of GCLKs:                        2  out of     16    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 10    |
hs_OBUF(u4_hs:O)                   | NONE(*)(u4_vlocbuf_4)  | 11    |
u0_recclk:Q                        | NONE                   | 26    |
u4_vgaclk:Q                        | NONE                   | 10    |
u1_ramclk(u1_Mmux_ramclk_Result1:O)| NONE(*)(u1_u0/B215)    | 46    |
u4_vlocbuf_9:Q                     | NONE                   | 10    |
u4_vlocbuf_9_1:Q                   | NONE                   | 12    |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 5.567ns (Maximum Frequency: 179.630MHz)
   Minimum input arrival time before clock: 6.029ns
   Maximum output required time after clock: 8.592ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               3.938ns (Levels of Logic = 8)
  Source:            u0_divcnt_0 (FF)
  Destination:       u0_divcnt_6 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: u0_divcnt_0 to u0_divcnt_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.568   0.724  u0_divcnt_0 (u0_divcnt_0)
     LUT1_L:I0->LO         2   0.439   0.000  u0_divcnt_Madd__n0000_inst_lut2_01 (u0_divcnt_Madd__n0000_inst_lut2_0)
     MUXCY:S->O            1   0.298   0.000  u0_divcnt_Madd__n0000_inst_cy_0 (u0_divcnt_Madd__n0000_inst_cy_0)
     MUXCY:CI->O           1   0.053   0.000  u0_divcnt_Madd__n0000_inst_cy_1 (u0_divcnt_Madd__n0000_inst_cy_1)
     MUXCY:CI->O           1   0.053   0.000  u0_divcnt_Madd__n0000_inst_cy_2 (u0_divcnt_Madd__n0000_inst_cy_2)
     MUXCY:CI->O           1   0.053   0.000  u0_divcnt_Madd__n0000_inst_cy_3 (u0_divcnt_Madd__n0000_inst_cy_3)
     MUXCY:CI->O           1   0.053   0.000  u0_divcnt_Madd__n0000_inst_cy_4 (u0_divcnt_Madd__n0000_inst_cy_4)
     MUXCY:CI->O           0   0.053   0.000  u0_divcnt_Madd__n0000_inst_cy_5 (u0_divcnt_Madd__n0000_inst_cy_5)
     XORCY:CI->O           1   1.274   0.000  u0_divcnt_Madd__n0000_inst_sum_6 (u0_divcnt__n0000<6>)
     FDR:D                     0.370          u0_divcnt_6
    ----------------------------------------
    Total                      3.938ns (3.214ns logic, 0.724ns route)
                                       (81.6% logic, 18.4% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u4_hs:O'
Delay:               5.567ns (Levels of Logic = 13)
  Source:            u4_vlocbuf_9 (FF)
  Destination:       u4_vlocbuf_9 (FF)
  Source Clock:      u4_hs:O rising
  Destination Clock: u4_hs:O rising

  Data Path: u4_vlocbuf_9 to u4_vlocbuf_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q           14   0.568   0.977  u4_vlocbuf_9 (u4_vlocbuf_9)
     LUT4:I0->O            3   0.439   0.724  u4__n000411 (CHOICE732)
     LUT4_D:I0->LO         1   0.439   0.000  u4__n000434 (N12987)
     MUXCY:S->O            1   0.298   0.000  u4_vlocbuf_inst_cy_7 (u4_vlocbuf_inst_cy_7)
     MUXCY:CI->O           1   0.053   0.000  u4_vlocbuf_inst_cy_8 (u4_vlocbuf_inst_cy_8)
     MUXCY:CI->O           1   0.053   0.000  u4_vlocbuf_inst_cy_9 (u4_vlocbuf_inst_cy_9)
     MUXCY:CI->O           1   0.053   0.000  u4_vlocbuf_inst_cy_10 (u4_vlocbuf_inst_cy_10)
     MUXCY:CI->O           1   0.053   0.000  u4_vlocbuf_inst_cy_11 (u4_vlocbuf_inst_cy_11)