📄 xianshi.rpt
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Device-Specific Information: d:\111\xianshi.rpt
xianshi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 12/ 96( 12%) 8/ 48( 16%) 0/ 48( 0%) 7/16( 43%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\111\xianshi.rpt
xianshi
** EQUATIONS **
d10 : INPUT;
d11 : INPUT;
d12 : INPUT;
d13 : INPUT;
d20 : INPUT;
d21 : INPUT;
d22 : INPUT;
d23 : INPUT;
d30 : INPUT;
d31 : INPUT;
d32 : INPUT;
d33 : INPUT;
d40 : INPUT;
d41 : INPUT;
d42 : INPUT;
d43 : INPUT;
sel0 : INPUT;
sel1 : INPUT;
sel2 : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC1_B3;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC6_B11;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC1_B11;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC3_B3;
-- Node name is ':129'
-- Equation name is '_LC8_B11', type is buried
!_LC8_B11 = _LC8_B11~NOT;
_LC8_B11~NOT = LCELL( _EQ001);
_EQ001 = !sel2
# !sel1
# sel0;
-- Node name is ':139'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ002);
_EQ002 = sel0 & sel1 & sel2;
-- Node name is ':142'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = LCELL( _EQ003);
_EQ003 = d43 & !_LC3_B11
# !_LC3_B11 & !_LC8_B11
# d33 & _LC3_B11;
-- Node name is ':149'
-- Equation name is '_LC5_B11', type is buried
!_LC5_B11 = _LC5_B11~NOT;
_LC5_B11~NOT = LCELL( _EQ004);
_EQ004 = sel2
# sel1
# !sel0;
-- Node name is ':152'
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = LCELL( _EQ005);
_EQ005 = d23 & _LC5_B11
# !_LC5_B11 & _LC7_B3;
-- Node name is ':159'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ006);
_EQ006 = !sel0 & !sel1 & !sel2;
-- Node name is ':162'
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = LCELL( _EQ007);
_EQ007 = !_LC2_B11 & _LC8_B3
# d13 & _LC2_B11;
-- Node name is ':171'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ008);
_EQ008 = d42 & !_LC3_B11
# !_LC3_B11 & !_LC8_B11
# d32 & _LC3_B11;
-- Node name is ':174'
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = LCELL( _EQ009);
_EQ009 = d22 & _LC5_B11
# _LC4_B11 & !_LC5_B11;
-- Node name is ':177'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ010);
_EQ010 = !_LC2_B11 & _LC7_B11
# d12 & _LC2_B11;
-- Node name is ':186'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = LCELL( _EQ011);
_EQ011 = d41 & !_LC3_B11
# !_LC3_B11 & !_LC8_B11
# d31 & _LC3_B11;
-- Node name is ':189'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = LCELL( _EQ012);
_EQ012 = d21 & _LC5_B11
# !_LC5_B11 & _LC6_B3;
-- Node name is ':192'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = LCELL( _EQ013);
_EQ013 = _LC2_B3 & !_LC2_B11
# d11 & _LC2_B11;
-- Node name is ':201'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = LCELL( _EQ014);
_EQ014 = !_LC3_B11 & !_LC8_B11
# d40 & !_LC3_B11
# d30 & _LC3_B11;
-- Node name is ':204'
-- Equation name is '_LC5_B3', type is buried
_LC5_B3 = LCELL( _EQ015);
_EQ015 = d20 & _LC5_B11
# _LC4_B3 & !_LC5_B11;
-- Node name is ':207'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ016);
_EQ016 = !_LC2_B11 & _LC5_B3
# d10 & _LC2_B11;
Project Information d:\111\xianshi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,506K
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