📄 qiangdaqi.rpt
字号:
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\qingdaqi1\qiangdaqi.rpt
qiangdaqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 3/ 96( 3%) 1/ 48( 2%) 2/ 48( 4%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 13/ 96( 13%) 2/ 48( 4%) 33/ 48( 68%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
E: 3/ 96( 3%) 0/ 48( 0%) 0/ 48( 0%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
F: 30/ 96( 31%) 0/ 48( 0%) 28/ 48( 58%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 6/24( 25%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\qingdaqi1\qiangdaqi.rpt
qiangdaqi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 37 clk
DFF 9 |CHOOSE:11|:3
INPUT 3 clk1
LCELL 1 :52
Device-Specific Information: d:\qingdaqi1\qiangdaqi.rpt
qiangdaqi
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 10 start
Device-Specific Information: d:\qingdaqi1\qiangdaqi.rpt
qiangdaqi
** EQUATIONS **
clk : INPUT;
clk1 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
p : INPUT;
start : INPUT;
s0 : INPUT;
s1 : INPUT;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC4_C19;
-- Node name is 'dw'
-- Equation name is 'dw', type is output
dw = _LC1_F21;
-- Node name is 'p0'
-- Equation name is 'p0', type is output
p0 = _LC7_F5;
-- Node name is 'p1'
-- Equation name is 'p1', type is output
p1 = _LC4_F5;
-- Node name is 'p2'
-- Equation name is 'p2', type is output
p2 = _LC5_F5;
-- Node name is 'p3'
-- Equation name is 'p3', type is output
p3 = GND;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC4_F18;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC7_F17;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC5_F17;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC4_F15;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _LC5_F16;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = _LC7_F14;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = _LC8_F14;
-- Node name is 'ss0'
-- Equation name is 'ss0', type is output
ss0 = _LC4_B19;
-- Node name is 'ss1'
-- Equation name is 'ss1', type is output
ss1 = _LC2_B19;
-- Node name is 'ss2'
-- Equation name is 'ss2', type is output
ss2 = _LC6_B19;
-- Node name is 'ss3'
-- Equation name is 'ss3', type is output
ss3 = _LC1_B19;
-- Node name is 'ss4'
-- Equation name is 'ss4', type is output
ss4 = _LC8_B19;
-- Node name is '|CHOOSE:11|:3'
-- Equation name is '_LC1_F16', type is buried
_LC1_F16 = DFFE( VCC, _LC6_F16, start, VCC, VCC);
-- Node name is '|C60:24|:17' = '|C60:24|dw0'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = DFFE( _EQ001, clk, VCC, VCC, VCC);
_EQ001 = _LC1_F5 & !p
# _LC1_F5 & !_LC4_C13 & !_LC5_C21;
-- Node name is '|C60:24|:16' = '|C60:24|dw1'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = DFFE( _EQ002, clk, VCC, VCC, VCC);
_EQ002 = !_LC1_C13 & _LC3_C13 & _LC4_C13 & _LC7_C23
# !_LC1_C13 & !_LC3_C13 & !_LC4_C13 & _LC7_C23;
-- Node name is '|C60:24|:15' = '|C60:24|dw2'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = DFFE( _EQ003, clk, VCC, VCC, VCC);
_EQ003 = _LC4_C13 & _LC7_C13 & _LC8_C13
# _LC3_C13 & _LC7_C13 & _LC8_C13
# !_LC3_C13 & !_LC4_C13 & _LC7_C13 & !_LC8_C13;
-- Node name is '|C60:24|:14' = '|C60:24|dw3'
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = DFFE( _EQ004, clk, VCC, VCC, VCC);
_EQ004 = _LC1_F5 & !p
# _LC1_F5 & !_LC5_C21 & _LC6_C13;
-- Node name is '|C60:24|:21' = '|C60:24|gw0'
-- Equation name is '_LC4_C22', type is buried
_LC4_C22 = DFFE( _EQ005, clk, VCC, VCC, VCC);
_EQ005 = _LC1_F5 & !p
# _LC1_F5 & !_LC5_C21 & _LC7_C22;
-- Node name is '|C60:24|:20' = '|C60:24|gw1'
-- Equation name is '_LC3_C22', type is buried
_LC3_C22 = DFFE( _EQ006, clk, VCC, VCC, VCC);
_EQ006 = _LC1_C22 & _LC3_C22 & _LC4_C22
# _LC1_C13 & _LC1_C22 & !_LC3_C22 & !_LC4_C22
# !_LC1_C13 & _LC1_C22 & _LC3_C22;
-- Node name is '|C60:24|:19' = '|C60:24|gw2'
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = DFFE( _EQ007, clk, VCC, VCC, VCC);
_EQ007 = _LC1_F5 & !p
# _LC1_F5 & !_LC5_C21 & _LC6_C22;
-- Node name is '|C60:24|:18' = '|C60:24|gw3'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = DFFE( _EQ008, clk, VCC, VCC, VCC);
_EQ008 = _LC1_C22 & _LC5_C22 & _LC7_C21
# _LC1_C13 & _LC1_C22 & !_LC5_C22 & !_LC7_C21
# !_LC1_C13 & _LC1_C22 & _LC7_C21;
-- Node name is '|C60:24|LPM_ADD_SUB:81|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = LCELL( _EQ009);
_EQ009 = _LC2_C22
# _LC3_C22
# _LC4_C22;
-- Node name is '|C60:24|:4'
-- Equation name is '_LC6_C19', type is buried
_LC6_C19 = DFFE( _EQ010, clk, VCC, VCC, VCC);
_EQ010 = _LC1_F5 & _LC6_C19 & p
# _LC1_F5 & _LC5_C21 & p;
-- Node name is '|C60:24|:69'
-- Equation name is '_LC5_C21', type is buried
!_LC5_C21 = _LC5_C21~NOT;
_LC5_C21~NOT = LCELL( _EQ011);
_EQ011 = _LC7_C21
# _LC5_C22
# !_LC1_C13;
-- Node name is '|C60:24|:70'
-- Equation name is '_LC1_C13', type is buried
!_LC1_C13 = _LC1_C13~NOT;
_LC1_C13~NOT = LCELL( _EQ012);
_EQ012 = _LC5_C13
# _LC8_C13
# _LC4_C13
# _LC3_C13;
-- Node name is '|C60:24|:108'
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = LCELL( _EQ013);
_EQ013 = !_LC3_C13 & !_LC4_C13 & !_LC5_C13 & !_LC8_C13
# _LC4_C13 & _LC5_C13
# _LC3_C13 & _LC5_C13
# _LC5_C13 & _LC8_C13;
-- Node name is '|C60:24|:153'
-- Equation name is '_LC6_C22', type is buried
_LC6_C22 = LCELL( _EQ014);
_EQ014 = _LC2_C22 & _LC3_C22
# _LC2_C22 & _LC4_C22
# _LC1_C13 & !_LC2_C22 & !_LC3_C22 & !_LC4_C22
# !_LC1_C13 & _LC2_C22;
-- Node name is '|C60:24|:171'
-- Equation name is '_LC7_C22', type is buried
_LC7_C22 = LCELL( _EQ015);
_EQ015 = !_LC1_C13 & _LC4_C22
# _LC1_C13 & !_LC4_C22;
-- Node name is '|C60:24|~265~1'
-- Equation name is '_LC7_C13', type is buried
-- synthesized logic cell
_LC7_C13 = LCELL( _EQ016);
_EQ016 = !_LC1_C13 & _LC7_C23;
-- Node name is '|C60:24|~283~1'
-- Equation name is '_LC7_C23', type is buried
-- synthesized logic cell
_LC7_C23 = LCELL( _EQ017);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -