📄 qiangdaqi.rpt
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Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 28/96 ( 29%)
Total logic cells used: 167/1152 ( 14%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 563/4608 ( 12%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 18
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 167
Total flipflops required: 46
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 25/1152 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 8/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 8 8 8 8 2 8 7 7 8 88/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 8 0 0 0 0 0 0 0 0 8 8 2 7 8 8 1 0 8 5 0 8 71/0
Total: 0 0 0 0 8 0 0 0 0 0 0 0 0 16 16 10 15 16 16 17 2 16 12 7 16 167/0
Device-Specific Information: d:\qingdaqi1\qiangdaqi.rpt
qiangdaqi
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
122 - - - 13 INPUT 0 0 0 37 clk
128 - - - 13 INPUT 0 0 0 3 clk1
72 - - - 03 INPUT 0 0 0 2 d1
73 - - - 01 INPUT 0 0 0 2 d2
78 - - F -- INPUT 0 0 0 2 d3
79 - - F -- INPUT 0 0 0 2 d4
83 - - E -- INPUT 0 0 0 18 p
86 - - E -- INPUT 0 0 0 10 start
87 - - E -- INPUT 0 0 0 28 s0
88 - - D -- INPUT 0 0 0 28 s1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\qingdaqi1\qiangdaqi.rpt
qiangdaqi
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - B -- OUTPUT 0 1 0 0 alarm
81 - - F -- OUTPUT 0 1 0 0 dw
95 - - B -- OUTPUT 0 1 0 0 p0
92 - - C -- OUTPUT 0 1 0 0 p1
91 - - C -- OUTPUT 0 1 0 0 p2
90 - - C -- OUTPUT 0 0 0 0 p3
43 - - - 18 OUTPUT 0 1 0 0 q0
44 - - - 18 OUTPUT 0 1 0 0 q1
46 - - - 17 OUTPUT 0 1 0 0 q2
47 - - - 16 OUTPUT 0 1 0 0 q3
48 - - - 15 OUTPUT 0 1 0 0 q4
49 - - - 14 OUTPUT 0 1 0 0 q5
51 - - - 14 OUTPUT 0 1 0 0 q6
97 - - B -- OUTPUT 0 1 0 0 ss0
98 - - B -- OUTPUT 0 1 0 0 ss1
100 - - A -- OUTPUT 0 1 0 0 ss2
99 - - B -- OUTPUT 0 1 0 0 ss3
8 - - A -- OUTPUT 0 1 0 0 ss4
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\qingdaqi1\qiangdaqi.rpt
qiangdaqi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - F 16 DFFE 1 1 0 9 |CHOOSE:11|:3
- 5 - C 22 OR2 0 3 0 2 |C60:24|LPM_ADD_SUB:81|addcore:adder|pcarry2
- 6 - C 19 DFFE 2 2 0 1 |C60:24|:4
- 5 - C 13 DFFE 2 3 0 3 |C60:24|dw3 (|C60:24|:14)
- 8 - C 13 DFFE 1 3 0 3 |C60:24|dw2 (|C60:24|:15)
- 3 - C 13 DFFE 1 3 0 4 |C60:24|dw1 (|C60:24|:16)
- 4 - C 13 DFFE 2 2 0 5 |C60:24|dw0 (|C60:24|:17)
- 7 - C 21 DFFE 1 3 0 2 |C60:24|gw3 (|C60:24|:18)
- 2 - C 22 DFFE 2 3 0 3 |C60:24|gw2 (|C60:24|:19)
- 3 - C 22 DFFE 1 3 0 3 |C60:24|gw1 (|C60:24|:20)
- 4 - C 22 DFFE 2 3 0 5 |C60:24|gw0 (|C60:24|:21)
- 5 - C 21 OR2 ! 0 3 0 6 |C60:24|:69
- 1 - C 13 OR2 ! 0 4 0 7 |C60:24|:70
- 6 - C 13 OR2 0 4 0 1 |C60:24|:108
- 6 - C 22 OR2 0 4 0 1 |C60:24|:153
- 7 - C 22 OR2 0 2 0 1 |C60:24|:171
- 7 - C 13 AND2 s 0 2 0 1 |C60:24|~265~1
- 7 - C 23 AND2 s 1 1 0 11 |C60:24|~283~1
- 1 - C 22 AND2 s 0 2 0 2 |C60:24|~283~2
- 3 - F 13 AND2 s 0 3 0 3 |DISP:18|~293~1
- 5 - F 18 OR2 ! 0 2 0 6 |DISP:18|:317
- 4 - F 17 AND2 0 2 0 1 |DISP:18|:329
- 4 - F 14 OR2 s 0 3 0 4 |DISP:18|~344~1
- 1 - F 18 AND2 0 4 0 5 |DISP:18|:353
- 3 - F 18 OR2 s ! 0 3 0 3 |DISP:18|~365~1
- 6 - F 14 OR2 0 4 0 1 |DISP:18|:370
- 2 - F 18 OR2 s ! 0 3 0 6 |DISP:18|~377~1
- 2 - F 17 AND2 0 2 0 1 |DISP:18|:377
- 6 - F 18 OR2 s 0 3 0 3 |DISP:18|~389~1
- 3 - F 14 OR2 ! 0 2 0 5 |DISP:18|:389
- 8 - F 18 OR2 ! 0 4 0 5 |DISP:18|:401
- 8 - F 14 OR2 0 4 1 0 |DISP:18|:404
- 5 - F 14 OR2 0 3 0 1 |DISP:18|:430
- 7 - F 14 OR2 0 4 1 0 |DISP:18|:440
- 8 - F 17 OR2 s 0 3 0 1 |DISP:18|~467~1
- 1 - F 17 OR2 0 3 0 1 |DISP:18|:467
- 5 - F 16 OR2 0 4 1 0 |DISP:18|:476
- 1 - F 19 AND2 0 1 0 5 |DISP:18|:488
- 1 - F 14 OR2 0 4 0 1 |DISP:18|:505
- 4 - F 15 OR2 0 4 1 0 |DISP:18|:512
- 3 - F 17 OR2 s 0 4 0 2 |DISP:18|~544~1
- 6 - F 17 OR2 0 4 0 1 |DISP:18|:544
- 5 - F 17 OR2 0 4 1 0 |DISP:18|:548
- 2 - F 14 OR2 0 4 0 1 |DISP:18|:572
- 7 - F 17 OR2 0 4 1 0 |DISP:18|:584
- 2 - F 16 OR2 s ! 0 3 0 4 |DISP:18|~614~1
- 6 - F 13 AND2 s 0 4 0 1 |DISP:18|~622~1
- 7 - F 24 AND2 s 0 4 0 1 |DISP:18|~622~2
- 8 - F 24 OR2 s 0 4 0 1 |DISP:18|~622~3
- 1 - F 24 OR2 s 0 4 0 1 |DISP:18|~622~4
- 7 - F 13 OR2 s 0 4 0 1 |DISP:18|~622~5
- 2 - F 13 OR2 s 0 4 0 1 |DISP:18|~622~6
- 1 - F 15 AND2 s 0 2 0 3 |DISP:18|~622~7
- 7 - F 18 OR2 s 0 4 0 1 |DISP:18|~622~8
- 4 - F 18 OR2 0 4 1 0 |DISP:18|:622
- 1 - C 18 OR2 0 2 0 1 |HALFMIN:26|LPM_ADD_SUB:81|addcore:adder|pcarry1
- 6 - C 18 OR2 0 3 0 2 |HALFMIN:26|LPM_ADD_SUB:81|addcore:adder|pcarry2
- 6 - C 15 OR2 0 2 0 1 |HALFMIN:26|LPM_ADD_SUB:86|addcore:adder|pcarry1
- 7 - C 19 DFFE 2 2 0 1 |HALFMIN:26|:4
- 7 - C 15 DFFE 2 3 0 3 |HALFMIN:26|dw3 (|HALFMIN:26|:14)
- 3 - C 15 DFFE 1 3 0 3 |HALFMIN:26|dw2 (|HALFMIN:26|:15)
- 5 - C 15 DFFE 1 3 0 4 |HALFMIN:26|dw1 (|HALFMIN:26|:16)
- 2 - C 15 DFFE 2 2 0 5 |HALFMIN:26|dw0 (|HALFMIN:26|:17)
- 3 - C 18 DFFE 1 3 0 2 |HALFMIN:26|gw3 (|HALFMIN:26|:18)
- 2 - C 18 DFFE 1 3 0 2 |HALFMIN:26|gw2 (|HALFMIN:26|:19)
- 5 - C 18 DFFE 2 3 0 4 |HALFMIN:26|gw1 (|HALFMIN:26|:20)
- 4 - C 18 DFFE 1 2 0 4 |HALFMIN:26|gw0 (|HALFMIN:26|:21)
- 8 - C 18 OR2 ! 0 3 0 5 |HALFMIN:26|:69
- 1 - C 15 AND2 0 4 0 7 |HALFMIN:26|:70
- 8 - C 15 OR2 0 4 0 1 |HALFMIN:26|:108
- 7 - C 18 OR2 0 3 0 1 |HALFMIN:26|:162
- 8 - C 23 AND2 s 0 2 0 3 |HALFMIN:26|~283~1
- 6 - F 05 DFFE 2 1 0 3 |LOCK:8|:7
- 8 - F 05 DFFE 2 1 0 3 |LOCK:8|:9
- 3 - F 05 DFFE 2 1 0 3 |LOCK:8|:11
- 2 - F 05 DFFE 2 1 0 3 |LOCK:8|:13
- 1 - F 05 DFFE 1 1 0 18 |LOCK:8|:15
- 3 - C 16 OR2 0 2 0 1 |M100:14|LPM_ADD_SUB:85|addcore:adder|pcarry1
- 1 - C 24 OR2 0 2 0 3 |M100:14|LPM_ADD_SUB:90|addcore:adder|pcarry1
- 5 - C 19 DFFE 2 2 0 1 |M100:14|:4
- 4 - C 17 DFFE 2 3 0 3 |M100:14|dw3 (|M100:14|:18)
- 5 - C 17 DFFE 1 3 0 3 |M100:14|dw2 (|M100:14|:19)
- 2 - C 24 DFFE 1 3 0 2 |M100:14|dw1 (|M100:14|:20)
- 1 - C 19 DFFE 2 2 0 3 |M100:14|dw0 (|M100:14|:21)
- 6 - C 21 DFFE 1 2 0 3 |M100:14|gw3 (|M100:14|:22)
- 6 - C 16 DFFE 1 3 0 2 |M100:14|gw2 (|M100:14|:23)
- 7 - C 16 DFFE 1 3 0 3 |M100:14|gw1 (|M100:14|:24)
- 2 - C 19 DFFE 2 3 0 5 |M100:14|gw0 (|M100:14|:25)
- 8 - C 21 OR2 ! 0 2 0 6 |M100:14|:73
- 8 - C 17 OR2 ! 0 3 0 6 |M100:14|:74
- 3 - C 17 OR2 0 3 0 1 |M100:14|:112
- 3 - C 19 OR2 0 2 0 1 |M100:14|:175
- 4 - C 16 OR2 s 0 4 0 2 |M100:14|~287~1
- 4 - C 21 OR2 s 1 3 0 1 |M100:14|~287~2
- 1 - C 17 AND2 s 0 2 0 2 |M100:14|~293~1
- 3 - C 21 OR2 2 2 0 1 |SELLING1:34|:256
- 2 - C 21 OR2 2 2 0 1 |SELLING1:34|:258
- 1 - C 21 OR2 2 2 0 3 |SELLING1:34|:262
- 1 - C 20 OR2 2 2 0 1 |SELLING1:34|:274
- 2 - C 20 OR2 2 2 0 1 |SELLING1:34|:276
- 5 - C 16 OR2 2 2 0 3 |SELLING1:34|:277
- 2 - C 16 OR2 2 2 0 1 |SELLING1:34|:289
- 1 - C 16 OR2 2 2 0 1 |SELLING1:34|:291
- 8 - C 16 OR2 2 2 0 2 |SELLING1:34|:292
- 5 - F 24 OR2 2 2 0 1 |SELLING1:34|:304
- 4 - F 24 OR2 2 2 0 1 |SELLING1:34|:306
- 6 - F 24 OR2 2 2 0 3 |SELLING1:34|:307
- 2 - C 23 OR2 2 2 0 1 |SELLING1:34|:316
- 3 - C 23 OR2 2 2 0 1 |SELLING1:34|:318
- 2 - C 17 OR2 2 2 0 3 |SELLING1:34|:322
- 6 - C 17 OR2 2 2 0 1 |SELLING1:34|:324
- 4 - C 14 OR2 2 2 0 1 |SELLING1:34|:331
- 8 - C 14 OR2 2 2 0 1 |SELLING1:34|:333
- 7 - C 17 OR2 2 2 0 3 |SELLING1:34|:337
- 2 - C 13 OR2 2 2 0 1 |SELLING1:34|:339
- 4 - C 15 OR2 2 2 0 1 |SELLING1:34|:346
- 5 - C 14 OR2 2 2 0 1 |SELLING1:34|:348
- 3 - C 24 OR2 2 2 0 2 |SELLING1:34|:352
- 4 - C 24 OR2 2 2 0 1 |SELLING1:34|:354
- 6 - C 24 OR2 2 2 0 1 |SELLING1:34|:361
- 5 - C 24 OR2 2 2 0 1 |SELLING1:34|:363
- 8 - C 24 OR2 2 2 0 3 |SELLING1:34|:367
- 7 - C 24 OR2 2 2 0 1 |SELLING1:34|:369
- 7 - B 19 DFFE 1 2 0 5 |SHAOMIAOD:49|Q2 (|SHAOMIAOD:49|:31)
- 3 - B 19 DFFE 1 1 0 6 |SHAOMIAOD:49|Q1 (|SHAOMIAOD:49|:32)
- 5 - B 19 DFFE 1 0 0 7 |SHAOMIAOD:49|Q0 (|SHAOMIAOD:49|:33)
- 4 - B 19 AND2 0 3 1 5 |SHAOMIAOD:49|:82
- 2 - B 19 AND2 0 3 1 5 |SHAOMIAOD:49|:86
- 6 - B 19 AND2 0 3 1 6 |SHAOMIAOD:49|:90
- 1 - B 19 AND2 0 3 1 6 |SHAOMIAOD:49|:94
- 8 - B 19 AND2 0 3 1 6 |SHAOMIAOD:49|:137
- 3 - F 22 OR2 ! 0 4 0 1 |SHAOMIAOD:49|:250
- 4 - F 22 OR2 ! 0 4 0 1 |SHAOMIAOD:49|:262
- 5 - F 22 OR2 ! 0 2 0 7 |SHAOMIAOD:49|:270
- 2 - F 24 OR2 ! 0 4 0 1 |SHAOMIAOD:49|:277
- 5 - F 13 OR2 ! 0 4 0 2 |SHAOMIAOD:49|:283
- 4 - F 13 OR2 ! 0 3 0 12 |SHAOMIAOD:49|:286
- 7 - F 16 OR2 0 4 0 1 |SHAOMIAOD:49|:295
- 3 - F 16 OR2 0 3 0 2 |SHAOMIAOD:49|:298
- 8 - F 13 OR2 0 2 0 2 |SHAOMIAOD:49|:301
- 1 - F 13 OR2 0 3 0 6 |SHAOMIAOD:49|:304
- 3 - F 24 OR2 0 4 0 1 |SHAOMIAOD:49|:313
- 2 - F 22 OR2 0 3 0 2 |SHAOMIAOD:49|:316
- 1 - F 22 OR2 0 4 0 6 |SHAOMIAOD:49|:322
- 1 - C 14 OR2 0 2 0 1 |S10:36|LPM_ADD_SUB:51|addcore:adder|pcarry1
- 2 - C 14 OR2 0 3 0 2 |S10:36|LPM_ADD_SUB:51|addcore:adder|pcarry2
- 8 - C 19 DFFE 2 2 0 1 |S10:36|:4
- 5 - C 23 DFFE 1 2 0 3 |S10:36|dw3 (|S10:36|:14)
- 3 - C 14 DFFE 1 3 0 2 |S10:36|dw2 (|S10:36|:15)
- 7 - C 14 DFFE 1 3 0 3 |S10:36|dw1 (|S10:36|:16)
- 6 - C 14 DFFE 2 2 0 4 |S10:36|dw0 (|S10:36|:17)
- 1 - C 23 OR2 ! 0 2 0 5 |S10:36|:40
- 4 - C 23 OR2 1 3 0 1 |S10:36|:106
- 6 - F 21 OR2 0 4 0 1 |S10:43|LPM_ADD_SUB:51|addcore:adder|:69
- 1 - F 21 DFFE 2 2 1 1 |S10:43|:4
- 5 - F 21 DFFE 2 3 0 4 |S10:43|dw3 (|S10:43|:14)
- 4 - F 21 DFFE 1 3 0 4 |S10:43|dw2 (|S10:43|:15)
- 2 - F 21 DFFE 1 2 0 4 |S10:43|dw1 (|S10:43|:16)
- 3 - F 21 DFFE 2 2 0 6 |S10:43|dw0 (|S10:43|:17)
- 7 - F 21 OR2 ! 0 4 0 4 |S10:43|:40
- 8 - F 21 AND2 s 1 2 0 2 |S10:43|~152~1
- 5 - F 05 AND2 0 4 1 1 |TANSF:13|:160
- 4 - F 05 OR2 0 4 1 1 |TANSF:13|:175
- 7 - F 05 OR2 0 4 1 1 |TANSF:13|:188
- 4 - F 16 OR2 s 3 0 0 1 ~10~1
- 4 - C 19 OR2 0 4 1 0 :30
- 6 - F 16 OR2 1 2 0 1 :52
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