lock.vhd

来自「VHDL电子抢答器的实现。有多个文件」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
entity lock is
port (d1,d2,d3,d4:in std_logic;
		clk,clr:in std_logic;
		q1,q2,q3,q4,alm:out std_logic);
end lock;
architecture b of lock is
begin
	process(clk)
	begin
		if clr='0'then
			q1<='0';
			q2<='0';
			q3<='0';
			q4<='0';
		elsif clk'event and clk='1'then
			q1<=d1;
			q2<=d2;
			q3<=d3;
			q4<=d4;
			alm<='1';
		end if;

	end process;

end b;