c60.vhd

VHDL电子抢答器的实现。有多个文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c60 is
port
(  en      : in  std_logic;
  eq       : in std_logic;
  clk      : in std_logic;
alarm      : out std_logic;
   h       : out std_logic_vector( 3 downto 0 );
   l       : out std_logic_vector( 3 downto 0 )
);
end c60;
architecture b of c60 is
begin
 process (clk, eq,en)--参数没什么用，可以删去
 variable gw,dw:std_logic_vector(3 downto 0);
begin
 	if clk'event and clk='1' then
		if eq='1'then
			if en='1'then
				if dw=0 and gw=0 then
					alarm<='1';
				elsif dw=0 then
					dw:="1001";
					gw:=gw-1;
				else
					dw:=dw-1;
				end if;
			else
				alarm<='0';
				gw:="0101";
				dw:="1001";
			end if;
		else
			alarm<='0';
			gw:="0000";
			dw:="0000";
		end if;
	end if;
	h<=gw;
	l<=dw;
 end process;
end b;