📄 ji.rpt
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_LC6_C22 = LCELL( _EQ026);
_EQ026 = _LC3_C22 & !_LC7_C15
# B13 & _LC7_C15;
-- Node name is ':257'
-- Equation name is '_LC8_C23', type is buried
!_LC8_C23 = _LC8_C23~NOT;
_LC8_C23~NOT = LCELL( _EQ027);
_EQ027 = !B42 & !q2
# !B42 & _LC2_C15
# !_LC2_C15 & !q2;
-- Node name is ':260'
-- Equation name is '_LC1_C23', type is buried
!_LC1_C23 = _LC1_C23~NOT;
_LC1_C23~NOT = LCELL( _EQ028);
_EQ028 = !B32 & !_LC8_C23
# !B32 & _LC4_C15
# !_LC4_C15 & !_LC8_C23;
-- Node name is ':263'
-- Equation name is '_LC6_C17', type is buried
!_LC6_C17 = _LC6_C17~NOT;
_LC6_C17~NOT = LCELL( _EQ029);
_EQ029 = !B22 & !_LC1_C23
# !B22 & _LC3_C15
# !_LC1_C23 & !_LC3_C15;
-- Node name is ':272'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = LCELL( _EQ030);
_EQ030 = !_LC2_C15 & q1
# B41 & _LC2_C15;
-- Node name is ':275'
-- Equation name is '_LC4_C19', type is buried
_LC4_C19 = LCELL( _EQ031);
_EQ031 = _LC2_C21 & !_LC4_C15
# B31 & _LC4_C15;
-- Node name is ':278'
-- Equation name is '_LC5_C19', type is buried
_LC5_C19 = LCELL( _EQ032);
_EQ032 = !_LC3_C15 & _LC4_C19
# B21 & _LC3_C15;
-- Node name is ':310'
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = LCELL( _EQ033);
_EQ033 = !q3
# _LC5_C23;
-- Node name is ':312'
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = LCELL( _EQ034);
_EQ034 = !q0 & !q1 & !q2;
-- Node name is ':371'
-- Equation name is '_LC3_C17', type is buried
!_LC3_C17 = _LC3_C17~NOT;
_LC3_C17~NOT = LCELL( _EQ035);
_EQ035 = _LC5_C22 & q0 & q1 & q2
# _LC5_C22 & !q1 & !q2
# _LC5_C22 & !q0 & !q2;
-- Node name is ':399'
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = LCELL( _EQ036);
_EQ036 = q3
# !_LC5_C23;
-- Node name is ':488'
-- Equation name is '_LC7_C22', type is buried
_LC7_C22 = LCELL( _EQ037);
_EQ037 = !ff & _LC6_C22
# ff & !_LC5_C23 & q3;
-- Node name is ':501'
-- Equation name is '_LC5_C17', type is buried
!_LC5_C17 = _LC5_C17~NOT;
_LC5_C17~NOT = LCELL( _EQ038);
_EQ038 = !_LC4_C17 & _LC8_C16 & q2
# _LC4_C17 & _LC8_C16 & !q2
# !ff;
-- Node name is ':502'
-- Equation name is '_LC8_C17', type is buried
!_LC8_C17 = _LC8_C17~NOT;
_LC8_C17~NOT = LCELL( _EQ039);
_EQ039 = !B12 & !_LC6_C17
# !B12 & _LC7_C15
# !_LC6_C17 & !_LC7_C15
# ff;
-- Node name is ':510'
-- Equation name is '_LC7_C19', type is buried
_LC7_C19 = LCELL( _EQ040);
_EQ040 = ff & _LC8_C16 & q0 & q1
# ff & _LC8_C16 & !q0 & !q1;
-- Node name is ':511'
-- Equation name is '_LC6_C19', type is buried
_LC6_C19 = LCELL( _EQ041);
_EQ041 = !ff & _LC5_C19 & !_LC7_C15
# B11 & !ff & _LC7_C15;
-- Node name is ':513'
-- Equation name is '_LC8_C19', type is buried
_LC8_C19 = LCELL( _EQ042);
_EQ042 = _LC5_C22 & !q0 & q1 & zf
# _LC5_C22 & q0 & !q1 & zf;
-- Node name is '~521~1'
-- Equation name is '~521~1', location is LC8_C21, type is buried.
-- synthesized logic cell
!_LC8_C21 = _LC8_C21~NOT;
_LC8_C21~NOT = LCELL( _EQ043);
_EQ043 = !B40 & !q0
# !B40 & _LC2_C15
# !_LC2_C15 & !q0;
-- Node name is '~521~2'
-- Equation name is '~521~2', location is LC5_C20, type is buried.
-- synthesized logic cell
!_LC5_C20 = _LC5_C20~NOT;
_LC5_C20~NOT = LCELL( _EQ044);
_EQ044 = !B30 & !_LC8_C21
# !B30 & _LC4_C15
# !_LC4_C15 & !_LC8_C21;
-- Node name is '~521~3'
-- Equation name is '~521~3', location is LC6_C20, type is buried.
-- synthesized logic cell
!_LC6_C20 = _LC6_C20~NOT;
_LC6_C20~NOT = LCELL( _EQ045);
_EQ045 = !B20 & !_LC5_C20
# !B20 & _LC3_C15
# !_LC3_C15 & !_LC5_C20;
-- Node name is '~521~4'
-- Equation name is '~521~4', location is LC7_C20, type is buried.
-- synthesized logic cell
!_LC7_C20 = _LC7_C20~NOT;
_LC7_C20~NOT = LCELL( _EQ046);
_EQ046 = !B10 & !_LC6_C20
# !B10 & _LC7_C15
# !_LC6_C20 & !_LC7_C15;
-- Node name is '~521~5'
-- Equation name is '~521~5', location is LC8_C20, type is buried.
-- synthesized logic cell
_LC8_C20 = LCELL( _EQ047);
_EQ047 = !_LC7_C20 & q0
# ff & q0
# q0 & zf
# !ff & !_LC7_C20 & !zf;
-- Node name is ':528'
-- Equation name is '_LC7_C15', type is buried
_LC7_C15 = LCELL( _EQ048);
_EQ048 = en0 & !en1 & !en2 & !en3;
-- Node name is ':537'
-- Equation name is '_LC3_C15', type is buried
_LC3_C15 = LCELL( _EQ049);
_EQ049 = !en0 & en1 & !en2 & !en3;
-- Node name is ':546'
-- Equation name is '_LC4_C15', type is buried
_LC4_C15 = LCELL( _EQ050);
_EQ050 = en0 & en1 & !en2 & !en3;
-- Node name is ':555'
-- Equation name is '_LC2_C15', type is buried
!_LC2_C15 = _LC2_C15~NOT;
_LC2_C15~NOT = LCELL( _EQ051);
_EQ051 = en1
# en0
# en3
# !en2;
-- Node name is '~681~1'
-- Equation name is '~681~1', location is LC7_C21, type is buried.
-- synthesized logic cell
_LC7_C21 = LCELL( _EQ052);
_EQ052 = !_LC2_C15
# _LC4_C15
# _LC7_C15
# _LC3_C15;
-- Node name is '~741~1'
-- Equation name is '~741~1', location is LC6_C21, type is buried.
-- synthesized logic cell
_LC6_C21 = LCELL( _EQ053);
_EQ053 = _LC7_C15
# _LC3_C15
# !_LC4_C15;
-- Node name is '~801~1'
-- Equation name is '~801~1', location is LC1_C15, type is buried.
-- synthesized logic cell
_LC1_C15 = LCELL( _EQ054);
_EQ054 = _LC7_C15
# !_LC3_C15;
Project Information d:\qingdaqi1\ji.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,123K
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