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📄 ji.rpt

📁 VHDL电子抢答器的实现。有多个文件
💻 RPT
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字号:
   -      6     -    C    22        OR2                0    3    0    1  :251
   -      8     -    C    23        OR2        !       0    3    0    1  :257
   -      1     -    C    23        OR2        !       0    3    0    1  :260
   -      6     -    C    17        OR2        !       0    3    0    1  :263
   -      2     -    C    21        OR2                0    3    0    1  :272
   -      4     -    C    19        OR2                0    3    0    1  :275
   -      5     -    C    19        OR2                0    3    0    1  :278
   -      5     -    C    22        OR2                0    2    0    3  :310
   -      5     -    C    23       AND2                0    3    0    3  :312
   -      3     -    C    17        OR2        !       0    4    0    1  :371
   -      8     -    C    16        OR2                0    2    0    2  :399
   -      7     -    C    22        OR2                1    3    0    1  :488
   -      5     -    C    17        OR2        !       1    3    0    1  :501
   -      8     -    C    17        OR2        !       1    3    0    1  :502
   -      7     -    C    19        OR2                1    3    0    1  :510
   -      6     -    C    19        OR2                1    3    0    1  :511
   -      8     -    C    19        OR2                1    3    0    1  :513
   -      8     -    C    21        OR2    s   !       0    3    0    1  ~521~1
   -      5     -    C    20        OR2    s   !       0    3    0    1  ~521~2
   -      6     -    C    20        OR2    s   !       0    3    0    1  ~521~3
   -      7     -    C    20        OR2    s   !       0    3    0    1  ~521~4
   -      8     -    C    20        OR2    s           2    2    0    1  ~521~5
   -      7     -    C    15       AND2                4    0    0   11  :528
   -      3     -    C    15       AND2                4    0    0    7  :537
   -      4     -    C    15       AND2                4    0    0    6  :546
   -      2     -    C    15        OR2        !       4    0    0    5  :555
   -      7     -    C    21        OR2    s           0    4    0    4  ~681~1
   -      6     -    C    21        OR2    s           0    3    0    4  ~741~1
   -      1     -    C    15        OR2    s           0    2    0    4  ~801~1


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                               d:\qingdaqi1\ji.rpt
ji

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:       8/ 96(  8%)     0/ 48(  0%)    18/ 48( 37%)    2/16( 12%)      4/16( 25%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                               d:\qingdaqi1\ji.rpt
ji

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       20         clk


Device-Specific Information:                               d:\qingdaqi1\ji.rpt
ji

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        5         clr


Device-Specific Information:                               d:\qingdaqi1\ji.rpt
ji

** EQUATIONS **

clk      : INPUT;
clr      : INPUT;
en0      : INPUT;
en1      : INPUT;
en2      : INPUT;
en3      : INPUT;
ff       : INPUT;
zf       : INPUT;

-- Node name is ':20' = 'B10' 
-- Equation name is 'B10', location is LC4_C20, type is buried.
B10      = DFFE( _EQ001, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ001 =  _LC7_C15 &  q0
         #  B10 & !_LC7_C15;

-- Node name is ':19' = 'B11' 
-- Equation name is 'B11', location is LC2_C19, type is buried.
B11      = DFFE( _EQ002, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ002 =  _LC7_C15 &  q1
         #  B11 & !_LC7_C15;

-- Node name is ':18' = 'B12' 
-- Equation name is 'B12', location is LC2_C17, type is buried.
B12      = DFFE( _EQ003, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ003 =  _LC7_C15 &  q2
         #  B12 & !_LC7_C15;

-- Node name is ':17' = 'B13' 
-- Equation name is 'B13', location is LC2_C22, type is buried.
B13      = DFFE( _EQ004, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ004 =  _LC7_C15 &  q3
         #  B13 & !_LC7_C15;

-- Node name is ':24' = 'B20' 
-- Equation name is 'B20', location is LC3_C20, type is buried.
B20      = DFFE( _EQ005, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ005 = !_LC1_C15 &  q0
         #  B20 &  _LC1_C15;

-- Node name is ':23' = 'B21' 
-- Equation name is 'B21', location is LC1_C19, type is buried.
B21      = DFFE( _EQ006, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ006 = !_LC1_C15 &  q1
         #  B21 &  _LC1_C15;

-- Node name is ':22' = 'B22' 
-- Equation name is 'B22', location is LC1_C17, type is buried.
B22      = DFFE( _EQ007, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ007 = !_LC1_C15 &  q2
         #  B22 &  _LC1_C15;

-- Node name is ':21' = 'B23' 
-- Equation name is 'B23', location is LC1_C22, type is buried.
B23      = DFFE( _EQ008, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ008 = !_LC1_C15 &  q3
         #  B23 &  _LC1_C15;

-- Node name is ':28' = 'B30' 
-- Equation name is 'B30', location is LC2_C20, type is buried.
B30      = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ009 = !_LC6_C21 &  q0
         #  B30 &  _LC6_C21;

-- Node name is ':27' = 'B31' 
-- Equation name is 'B31', location is LC6_C23, type is buried.
B31      = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ010 = !_LC6_C21 &  q1
         #  B31 &  _LC6_C21;

-- Node name is ':26' = 'B32' 
-- Equation name is 'B32', location is LC7_C23, type is buried.
B32      = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ011 = !_LC6_C21 &  q2
         #  B32 &  _LC6_C21;

-- Node name is ':25' = 'B33' 
-- Equation name is 'B33', location is LC4_C23, type is buried.
B33      = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ012 = !_LC6_C21 &  q3
         #  B33 &  _LC6_C21;

-- Node name is ':32' = 'B40' 
-- Equation name is 'B40', location is LC1_C21, type is buried.
B40      = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ013 = !_LC7_C21 &  q0
         #  B40 &  _LC7_C21;

-- Node name is ':31' = 'B41' 
-- Equation name is 'B41', location is LC5_C21, type is buried.
B41      = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ014 = !_LC7_C21 &  q1
         #  B41 &  _LC7_C21;

-- Node name is ':30' = 'B42' 
-- Equation name is 'B42', location is LC3_C23, type is buried.
B42      = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ015 = !_LC7_C21 &  q2
         #  B42 &  _LC7_C21;

-- Node name is ':29' = 'B43' 
-- Equation name is 'B43', location is LC3_C21, type is buried.
B43      = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC, !_LC2_C18);
  _EQ016 = !_LC7_C21 &  q3
         #  B43 &  _LC7_C21;

-- Node name is 'clr~1' 
-- Equation name is 'clr~1', location is LC2_C18, type is buried.
-- synthesized logic cell 
!_LC2_C18 = _LC2_C18~NOT;
_LC2_C18~NOT = LCELL(!clr);

-- Node name is 'fen0' 
-- Equation name is 'fen0', type is output 
fen0     =  q0;

-- Node name is 'fen1' 
-- Equation name is 'fen1', type is output 
fen1     =  q1;

-- Node name is 'fen2' 
-- Equation name is 'fen2', type is output 
fen2     =  q2;

-- Node name is 'fen3' 
-- Equation name is 'fen3', type is output 
fen3     =  q3;

-- Node name is ':16' = 'q0' 
-- Equation name is 'q0', location is LC1_C20, type is buried.
!q0      = q0~NOT;
q0~NOT   = DFFE( _EQ017, GLOBAL( clk), GLOBAL(!clr),  VCC,  VCC);
  _EQ017 =  _LC8_C20 & !q3
         #  _LC8_C20 & !zf;

-- Node name is ':15' = 'q1' 
-- Equation name is 'q1', location is LC3_C19, type is buried.
q1       = DFFE( _EQ018, GLOBAL( clk), GLOBAL(!clr),  VCC,  VCC);
  _EQ018 =  _LC6_C19 & !zf
         #  _LC7_C19 & !zf
         #  _LC8_C19;

-- Node name is ':14' = 'q2' 
-- Equation name is 'q2', location is LC7_C17, type is buried.
!q2      = q2~NOT;
q2~NOT   = DFFE( _EQ019, GLOBAL( clk), GLOBAL(!clr),  VCC,  VCC);
  _EQ019 = !_LC3_C17 & !_LC5_C17 & !_LC8_C17
         # !_LC3_C17 &  zf
         # !_LC5_C17 & !_LC8_C17 & !zf;

-- Node name is ':13' = 'q3' 
-- Equation name is 'q3', location is LC4_C22, type is buried.
q3       = DFFE( _EQ020, GLOBAL( clk), GLOBAL(!clr),  VCC,  VCC);
  _EQ020 =  _LC7_C22 & !zf
         #  _LC5_C22 &  _LC8_C22 &  zf;

-- Node name is '|LPM_ADD_SUB:339|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_C22', type is buried 
_LC8_C22 = LCELL( _EQ021);
  _EQ021 = !q1 &  q3
         # !q0 &  q3
         # !q2 &  q3
         #  q0 &  q1 &  q2 & !q3;

-- Node name is '|LPM_ADD_SUB:428|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_C17', type is buried 
_LC4_C17 = LCELL( _EQ022);
  _EQ022 =  q1
         #  q0;

-- Node name is ':233' 
-- Equation name is '_LC4_C21', type is buried 
_LC4_C21 = LCELL( _EQ023);
  _EQ023 = !_LC2_C15 &  q3
         #  B43 &  _LC2_C15;

-- Node name is ':239' 
-- Equation name is '_LC2_C23', type is buried 
_LC2_C23 = LCELL( _EQ024);
  _EQ024 = !_LC4_C15 &  _LC4_C21
         #  B33 &  _LC4_C15;

-- Node name is ':245' 
-- Equation name is '_LC3_C22', type is buried 
_LC3_C22 = LCELL( _EQ025);
  _EQ025 =  _LC2_C23 & !_LC3_C15
         #  B23 &  _LC3_C15;

-- Node name is ':251' 
-- Equation name is '_LC6_C22', type is buried 

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