s10.fit

VHDL电子抢答器的实现。有多个文件

-- MAX+plus II Compiler Fit File      
-- Version 10.1 06/12/2001            
-- Compiled: 12/12/2004 15:21:17      

-- Copyright (C) 1988-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "s10"
BEGIN

    DEVICE = "EPF10K10LC84-3";

    "clk"                          : INPUT_PIN  = 1      ;
    "en"                           : INPUT_PIN  = 2      ;
    "eq"                           : INPUT_PIN  = 42     ;
    "alarm"                        : OUTPUT_PIN = 36     ;
    "h0"                           : OUTPUT_PIN = 24     ;
    "h1"                           : OUTPUT_PIN = 64     ;
    "h2"                           : OUTPUT_PIN = 61     ;
    "h3"                           : OUTPUT_PIN = 52     ;
    "l0"                           : OUTPUT_PIN = 28     ;
    "l1"                           : OUTPUT_PIN = 30     ;
    "l2"                           : OUTPUT_PIN = 29     ;
    "l3"                           : OUTPUT_PIN = 62     ;
    "|LPM_ADD_SUB:51|addcore:adder|:69" : LOCATION   = LC7_C8 ;
    ":4"                           : LOCATION   = LC5_C8 ;
    ":14"                          : LOCATION   = LC1_C8 ;  -- dw3
    ":15"                          : LOCATION   = LC8_C8 ;  -- dw2
    ":16"                          : LOCATION   = LC6_C8 ;  -- dw1
    ":17"                          : LOCATION   = LC3_C8 ;  -- dw0
    ":40"                          : LOCATION   = LC2_C8 ;
    "~152~1"                       : LOCATION   = LC4_C8 ;

END;

INTERNAL_INFO "s10"
BEGIN
	DEVICE = EPF10K10LC84-3;
    OD4P1   : LORAX = "1:FB4->LC5_C8,->LC1_C8,->LC8_C8,->LC6_C8,->LC3_C8|";
    OD1P2   : LORAX = "1:FB1|2:FH1R2,PA20R2C7->LC5_C8,->LC1_C8,->LC3_C8,->LC4_C8||";
    OD3P42  : LORAX = "1:FB3|2:FH3R2,PA5R2C7->LC5_C8,->LC1_C8,->LC3_C8,->LC4_C8||";
    LC5_C8  : LORAX = "1:MSW5R2C6,V16C6->OV2C6P36|";
    LC1_C8  : LORAX = "1:MSW0R2C7,G38R2->OH0R2P62|";
    LC8_C8  : LORAX = "1:MSW4R2C6,HHL41R2->OH12R2P29|";
    LC6_C8  : LORAX = "1:MSW6R2C6,HHL29R2->OH14R2P30|";
    LC3_C8  : LORAX = "1:MSW2R2C7,HHL4R2->OH10R2P28|";
	LC7_C8  : LORAX2 = "LC1_C8, LC8_C8, LC6_C8, LC3_C8";
	LC5_C8  : LORAX2 = "OD1P2, LC5_C8, OD3P42, LC2_C8";
	LC1_C8  : LORAX2 = "OD1P2, OD3P42, LC7_C8, LC2_C8";
	LC8_C8  : LORAX2 = "LC8_C8, LC6_C8, LC4_C8, LC3_C8";
	LC6_C8  : LORAX2 = "X, LC6_C8, LC3_C8, LC4_C8";
	LC3_C8  : LORAX2 = "OD1P2, OD3P42, LC2_C8, LC3_C8";
	LC2_C8  : LORAX2 = "LC1_C8, LC8_C8, LC6_C8, LC3_C8";
	LC4_C8  : LORAX2 = "X, OD1P2, OD3P42, LC2_C8";
END;