study10.tdf

VHDL电子抢答器的实现。有多个文件

subdesign study10 
(
	en,eq,clk:input;
	alarm,h[3..0],l[3..0]:output;
)
variable 
	ss:machine of bits (l[3..0])
	with states(
		s0=0,
		s1=1,
     	s2=2,
		s3=3,
		s4=4,
		s5=5,
		s6=6,
		s7=7,
		s8=8,
		s9=9
);
begin
	ss.clk=clk;
l[]=9;
h[]=0;
if en==b"1"& eq==b"1"then
table
	ss => ss,l[],alarm;
    s9=>s8,8,0;
    s8=>s7,7,0;
    s7=>s6,6,0;
    s6=>s5,5,0;
    s5=>s4,4,0;
    s4=>s3,3,0;
    s3=>s2,2,0;
    s2=>s1,1,0;
    s1=>s0,0,1;
end table;
else alarm=b"0";
end if;
end;