📄 count10.rpt
字号:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\qingdaqi1\count10.rpt
count10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: d:\qingdaqi1\count10.rpt
count10
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clr
Device-Specific Information: d:\qingdaqi1\count10.rpt
count10
** EQUATIONS **
clk : INPUT;
clr : INPUT;
dn : INPUT;
en : INPUT;
up : INPUT;
-- Node name is 'dout0'
-- Equation name is 'dout0', type is output
dout0 = q0;
-- Node name is 'dout1'
-- Equation name is 'dout1', type is output
dout1 = q1;
-- Node name is 'dout2'
-- Equation name is 'dout2', type is output
dout2 = q2;
-- Node name is 'dout3'
-- Equation name is 'dout3', type is output
dout3 = q3;
-- Node name is ':13' = 'q0'
-- Equation name is 'q0', location is LC1_C8, type is buried.
!q0 = q0~NOT;
q0~NOT = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = !_LC3_C8 & !q0
# !en & !q0
# en & !_LC3_C8;
-- Node name is ':12' = 'q1'
-- Equation name is 'q1', location is LC2_C8, type is buried.
!q1 = q1~NOT;
q1~NOT = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = !_LC4_C8 & !_LC8_C8 & !q1
# !en & !q1
# en & !_LC4_C8 & !_LC8_C8;
-- Node name is ':11' = 'q2'
-- Equation name is 'q2', location is LC5_C7, type is buried.
q2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = en & _LC2_C7
# !en & q2;
-- Node name is ':10' = 'q3'
-- Equation name is 'q3', location is LC7_C7, type is buried.
q3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = en & _LC8_C7
# !en & q3;
-- Node name is '|LPM_ADD_SUB:97|addcore:adder|:76' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_C1', type is buried
_LC2_C1 = LCELL( _EQ005);
_EQ005 = !q1 & q2
# !q0 & q2
# q0 & q1 & !q2;
-- Node name is '|LPM_ADD_SUB:97|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC4_C7', type is buried
_LC4_C7 = LCELL( _EQ006);
_EQ006 = !q1 & q3
# !q0 & q3
# !q2 & q3
# q0 & q1 & q2 & !q3;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC5_C8', type is buried
!_LC5_C8 = _LC5_C8~NOT;
_LC5_C8~NOT = LCELL( _EQ007);
_EQ007 = !q0 & !q1;
-- Node name is ':63'
-- Equation name is '_LC6_C7', type is buried
_LC6_C7 = LCELL( _EQ008);
_EQ008 = !q3
# !_LC5_C8 & !q2;
-- Node name is ':65'
-- Equation name is '_LC6_C8', type is buried
!_LC6_C8 = _LC6_C8~NOT;
_LC6_C8~NOT = LCELL( _EQ009);
_EQ009 = q2
# _LC5_C8;
-- Node name is ':237'
-- Equation name is '_LC7_C8', type is buried
!_LC7_C8 = _LC7_C8~NOT;
_LC7_C8~NOT = LCELL( _EQ010);
_EQ010 = !q0 & q1 & q3
# !_LC6_C8 & !q0 & q1
# q0 & !q1 & q3
# !_LC6_C8 & q0 & !q1;
-- Node name is ':259'
-- Equation name is '_LC3_C7', type is buried
_LC3_C7 = LCELL( _EQ011);
_EQ011 = q2 & q3
# _LC5_C8 & q3
# !dn & q3;
-- Node name is ':265'
-- Equation name is '_LC8_C7', type is buried
_LC8_C7 = LCELL( _EQ012);
_EQ012 = _LC3_C7 & !up
# _LC4_C7 & _LC6_C7 & up;
-- Node name is ':271'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = LCELL( _EQ013);
_EQ013 = _LC5_C8 & q2
# dn & !_LC5_C8 & !q2 & q3
# !dn & q2;
-- Node name is ':274'
-- Equation name is '_LC2_C7', type is buried
_LC2_C7 = LCELL( _EQ014);
_EQ014 = _LC1_C7 & !up
# _LC2_C1 & _LC6_C7 & up;
-- Node name is ':284'
-- Equation name is '_LC4_C8', type is buried
!_LC4_C8 = _LC4_C8~NOT;
_LC4_C8~NOT = LCELL( _EQ015);
_EQ015 = _LC6_C7 & q0 & q1
# _LC6_C7 & !q0 & !q1
# !up;
-- Node name is ':285'
-- Equation name is '_LC8_C8', type is buried
!_LC8_C8 = _LC8_C8~NOT;
_LC8_C8~NOT = LCELL( _EQ016);
_EQ016 = !_LC7_C8 & !q1
# !dn & !q1
# dn & !_LC7_C8
# up;
-- Node name is ':292'
-- Equation name is '_LC3_C8', type is buried
!_LC3_C8 = _LC3_C8~NOT;
_LC3_C8~NOT = LCELL( _EQ017);
_EQ017 = q0 & !q3 & up
# dn & q0 & !q3
# dn & q0 & !up
# !dn & !q0 & !up;
Project Information d:\qingdaqi1\count10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,554K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -