tansf.vhd

来自「VHDL电子抢答器的实现。有多个文件」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
entity tansf is
port(d1,d2,d3,d4 : in std_logic;
		q : out std_logic_vector(3 downto 0));
end tansf;
architecture bb of tansf is
begin
	process(d1,d2,d3,d4)
	variable temp:std_logic_vector(3 downto 0);
	begin
		temp:=d1&d2&d3&d4;
		case temp is
			when "1000"=>q<="0001";
 			when "0100"=>q<="0010";
			when "0010"=>q<="0011";
			when "0001"=>q<="0100";
			when others=>q<="0000";--是15不显示
			end case;
	end process;
end bb;