zhonghe1.rpt
来自「VHDL电子抢答器的实现。有多个文件」· RPT 代码 · 共 671 行 · 第 1/2 页
RPT
671 行
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Device-Specific Information: d:\qingdaqi\zhonghe1.rpt
zhonghe1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 CP
Device-Specific Information: d:\qingdaqi\zhonghe1.rpt
zhonghe1
** EQUATIONS **
CP : INPUT;
djs0 : INPUT;
djs1 : INPUT;
djs2 : INPUT;
djs3 : INPUT;
d10 : INPUT;
d11 : INPUT;
d12 : INPUT;
d13 : INPUT;
d20 : INPUT;
d21 : INPUT;
d22 : INPUT;
d23 : INPUT;
d30 : INPUT;
d31 : INPUT;
d32 : INPUT;
d33 : INPUT;
d40 : INPUT;
d41 : INPUT;
d42 : INPUT;
d43 : INPUT;
-- Node name is ':33' = 'Q0'
-- Equation name is 'Q0', location is LC8_A1, type is buried.
Q0 = DFFE(!Q0, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':32' = 'Q1'
-- Equation name is 'Q1', location is LC7_A1, type is buried.
Q1 = DFFE( _EQ001, GLOBAL( CP), VCC, VCC, VCC);
_EQ001 = Q0 & !Q1
# !Q0 & Q1;
-- Node name is ':31' = 'Q2'
-- Equation name is 'Q2', location is LC4_A1, type is buried.
Q2 = DFFE( _EQ002, GLOBAL( CP), VCC, VCC, VCC);
_EQ002 = !Q0 & Q2
# !Q1 & Q2
# Q0 & Q1 & !Q2;
-- Node name is 'SEGOUT0'
-- Equation name is 'SEGOUT0', type is output
SEGOUT0 = _LC6_A2;
-- Node name is 'SEGOUT1'
-- Equation name is 'SEGOUT1', type is output
SEGOUT1 = _LC3_A2;
-- Node name is 'SEGOUT2'
-- Equation name is 'SEGOUT2', type is output
SEGOUT2 = _LC4_A3;
-- Node name is 'SEGOUT3'
-- Equation name is 'SEGOUT3', type is output
SEGOUT3 = _LC1_A3;
-- Node name is 'SELOUT0'
-- Equation name is 'SELOUT0', type is output
SELOUT0 = _LC5_A1;
-- Node name is 'SELOUT1'
-- Equation name is 'SELOUT1', type is output
SELOUT1 = _LC6_A1;
-- Node name is 'SELOUT2'
-- Equation name is 'SELOUT2', type is output
SELOUT2 = _LC3_A1;
-- Node name is 'SELOUT3'
-- Equation name is 'SELOUT3', type is output
SELOUT3 = _LC1_A1;
-- Node name is 'SELOUT4'
-- Equation name is 'SELOUT4', type is output
SELOUT4 = _LC2_A1;
-- Node name is ':188'
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ003);
_EQ003 = Q0 & !Q1 & !Q2;
-- Node name is ':192'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ004);
_EQ004 = !Q0 & Q1 & !Q2;
-- Node name is ':196'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ005);
_EQ005 = Q0 & Q1 & !Q2;
-- Node name is ':200'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ006);
_EQ006 = !Q0 & !Q1 & Q2;
-- Node name is ':204'
-- Equation name is '_LC5_A1', type is buried
!_LC5_A1 = _LC5_A1~NOT;
_LC5_A1~NOT = LCELL( _EQ007);
_EQ007 = !Q0
# Q1
# !Q2;
-- Node name is ':223'
-- Equation name is '_LC6_A3', type is buried
_LC6_A3 = LCELL( _EQ008);
_EQ008 = djs3 & !_LC2_A1
# !_LC2_A1 & !_LC5_A1
# d43 & _LC2_A1;
-- Node name is ':229'
-- Equation name is '_LC7_A3', type is buried
_LC7_A3 = LCELL( _EQ009);
_EQ009 = !_LC1_A1 & _LC6_A3
# d33 & _LC1_A1;
-- Node name is ':235'
-- Equation name is '_LC8_A3', type is buried
_LC8_A3 = LCELL( _EQ010);
_EQ010 = !_LC3_A1 & _LC7_A3
# d23 & _LC3_A1;
-- Node name is ':241'
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ011);
_EQ011 = !_LC6_A1 & _LC8_A3
# d13 & _LC6_A1;
-- Node name is ':250'
-- Equation name is '_LC5_A3', type is buried
_LC5_A3 = LCELL( _EQ012);
_EQ012 = djs2 & !_LC2_A1
# !_LC2_A1 & !_LC5_A1
# d42 & _LC2_A1;
-- Node name is ':253'
-- Equation name is '_LC2_A3', type is buried
_LC2_A3 = LCELL( _EQ013);
_EQ013 = !_LC1_A1 & _LC5_A3
# d32 & _LC1_A1;
-- Node name is ':256'
-- Equation name is '_LC3_A3', type is buried
_LC3_A3 = LCELL( _EQ014);
_EQ014 = _LC2_A3 & !_LC3_A1
# d22 & _LC3_A1;
-- Node name is ':259'
-- Equation name is '_LC4_A3', type is buried
_LC4_A3 = LCELL( _EQ015);
_EQ015 = _LC3_A3 & !_LC6_A1
# d12 & _LC6_A1;
-- Node name is ':268'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ016);
_EQ016 = djs1 & !_LC2_A1
# !_LC2_A1 & !_LC5_A1
# d41 & _LC2_A1;
-- Node name is ':271'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ017);
_EQ017 = !_LC1_A1 & _LC1_A2
# d31 & _LC1_A1;
-- Node name is ':274'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = LCELL( _EQ018);
_EQ018 = _LC2_A2 & !_LC3_A1
# d21 & _LC3_A1;
-- Node name is ':277'
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ019);
_EQ019 = _LC4_A2 & !_LC6_A1
# d11 & _LC6_A1;
-- Node name is ':286'
-- Equation name is '_LC5_A2', type is buried
_LC5_A2 = LCELL( _EQ020);
_EQ020 = djs0 & !_LC2_A1
# !_LC2_A1 & !_LC5_A1
# d40 & _LC2_A1;
-- Node name is ':289'
-- Equation name is '_LC7_A2', type is buried
_LC7_A2 = LCELL( _EQ021);
_EQ021 = !_LC1_A1 & _LC5_A2
# d30 & _LC1_A1;
-- Node name is ':292'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = LCELL( _EQ022);
_EQ022 = !_LC3_A1 & _LC7_A2
# d20 & _LC3_A1;
-- Node name is ':295'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = LCELL( _EQ023);
_EQ023 = !_LC6_A1 & _LC8_A2
# d10 & _LC6_A1;
Project Information d:\qingdaqi\zhonghe1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,908K
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