choose.vhd

来自「VHDL电子抢答器的实现。有多个文件」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;
entity choose is
	port(cp,clr:in std_logic;
			q:out std_logic);
end choose;
architecture b of choose is
begin
	process(cp,clr)
	begin
		if clr='0'then
			q<='0';
		elsif cp'event and cp='1'then
			q<='1';
		end if;
	end process;
end b;