s10.rpt
来自「VHDL电子抢答器的实现。有多个文件」· RPT 代码 · 共 528 行 · 第 1/2 页
RPT
528 行
- 6 - C 08 DFFE + 0 2 1 3 dw1 (:16)
- 3 - C 08 DFFE + 2 1 1 4 dw0 (:17)
- 2 - C 08 OR2 ! 0 4 0 4 :40
- 4 - C 08 AND2 s 2 1 0 2 ~152~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\111\s10.rpt
s10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\111\s10.rpt
s10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information: d:\111\s10.rpt
s10
** EQUATIONS **
clk : INPUT;
en : INPUT;
eq : INPUT;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC5_C8;
-- Node name is ':17' = 'dw0'
-- Equation name is 'dw0', location is LC3_C8, type is buried.
dw0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !en & eq
# !dw0 & eq & !_LC2_C8;
-- Node name is ':16' = 'dw1'
-- Equation name is 'dw1', location is LC6_C8, type is buried.
dw1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = dw0 & dw1 & _LC4_C8
# !dw0 & !dw1 & _LC4_C8;
-- Node name is ':15' = 'dw2'
-- Equation name is 'dw2', location is LC8_C8, type is buried.
dw2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = dw1 & dw2 & _LC4_C8
# dw0 & dw2 & _LC4_C8
# !dw0 & !dw1 & !dw2 & _LC4_C8;
-- Node name is ':14' = 'dw3'
-- Equation name is 'dw3', location is LC1_C8, type is buried.
dw3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = eq & !_LC2_C8 & !_LC7_C8
# !en & eq;
-- Node name is 'h0'
-- Equation name is 'h0', type is output
h0 = GND;
-- Node name is 'h1'
-- Equation name is 'h1', type is output
h1 = GND;
-- Node name is 'h2'
-- Equation name is 'h2', type is output
h2 = GND;
-- Node name is 'h3'
-- Equation name is 'h3', type is output
h3 = GND;
-- Node name is 'l0'
-- Equation name is 'l0', type is output
l0 = dw0;
-- Node name is 'l1'
-- Equation name is 'l1', type is output
l1 = dw1;
-- Node name is 'l2'
-- Equation name is 'l2', type is output
l2 = dw2;
-- Node name is 'l3'
-- Equation name is 'l3', type is output
l3 = dw3;
-- Node name is '|LPM_ADD_SUB:51|addcore:adder|:69' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C8', type is buried
_LC7_C8 = LCELL( _EQ005);
_EQ005 = !dw0 & !dw1 & !dw2 & dw3
# dw1 & !dw3
# dw0 & !dw3
# dw2 & !dw3;
-- Node name is ':4'
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = eq & _LC5_C8
# !en & eq
# eq & _LC2_C8;
-- Node name is ':40'
-- Equation name is '_LC2_C8', type is buried
!_LC2_C8 = _LC2_C8~NOT;
_LC2_C8~NOT = LCELL( _EQ007);
_EQ007 = dw3
# dw2
# dw1
# dw0;
-- Node name is '~152~1'
-- Equation name is '~152~1', location is LC4_C8, type is buried.
-- synthesized logic cell
_LC4_C8 = LCELL( _EQ008);
_EQ008 = en & eq & !_LC2_C8;
Project Information d:\111\s10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,594K
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