cout99.vhd

来自「VHDL电子抢答器的实现。有多个文件」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cout99 is
port(
		clk,en:in std_logic;
		h,l,c4:out std_logic_vector(3 downto 0);
		alarm:out std_logic);
end cout99;

architecture b of cout99 is
begin
	process(clk,en)
	variable gw,dw:std_logic_vector(3 downto 0);
	begin
		if(clk'event and clk='1'then
			if en='1'then
				if dw=0 and gw=0 then
					alarm<='1';
				elsif dw=0 then
					dw:="1001";
					gw:=gw-1;
				else
					dw:=dw-1;
				end if;
			else
				alarm<='0';
				gw:="1001";
				dw:="1001";
			end if;
		end if;
	h<=gw;
	l<=dw;
	c4="1110";
	end process;
end b;