sel.vhd

来自「VHDL电子抢答器的实现。有多个文件」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;
entity sel is
port(clk:in std_logic;
		a:out integer range 0 to 7);
end sel;
architecture b of sel is 
begin
	process(clk)
	variable aa:integer range 0 to 7;
	begin
		if clk'event and clk='1'then
		aa:=aa+1;
		end if;
		a<=aa;
--a随着aa的不断跳变也在0--7直间很快的改变
	end process;
end b;