lock.fit

来自「VHDL电子抢答器的实现。有多个文件」· FIT 代码 · 共 69 行

-- MAX+plus II Compiler Fit File      
-- Version 10.1 06/12/2001            
-- Compiled: 12/12/2004 00:12:05      

-- Copyright (C) 1988-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "lock"
BEGIN

    DEVICE = "EPF10K10LC84-3";

    "clk"                          : INPUT_PIN  = 1      ;
    "clr"                          : INPUT_PIN  = 2      ;
    "d1"                           : INPUT_PIN  = 43     ;
    "d2"                           : INPUT_PIN  = 84     ;
    "d3"                           : INPUT_PIN  = 44     ;
    "d4"                           : INPUT_PIN  = 42     ;
    "alm"                          : OUTPUT_PIN = 71     ;
    "q1"                           : OUTPUT_PIN = 18     ;
    "q2"                           : OUTPUT_PIN = 66     ;
    "q3"                           : OUTPUT_PIN = 30     ;
    "q4"                           : OUTPUT_PIN = 65     ;
    ":7"                           : LOCATION   = LC5_A1 ;
    ":9"                           : LOCATION   = LC2_B22;
    ":11"                          : LOCATION   = LC7_C7 ;
    ":13"                          : LOCATION   = LC5_B21;
    ":15"                          : LOCATION   = LC4_A20;

END;

INTERNAL_INFO "lock"
BEGIN
	DEVICE = EPF10K10LC84-3;
    OD4P1   : LORAX = "1:FB4->LC5_A1,->LC2_B22,->LC7_C7,->LC5_B21,->LC4_A20|";
    OD1P2   : LORAX = "1:FB1->LC5_A1,->LC2_B22,->LC7_C7,->LC5_B21|2:FH1R0,PA20R0C19->LC4_A20||";
    OD5P43  : LORAX = "1:FB5|2:CH1R0,PA7R0C0->LC5_A1||";
    OD0P84  : LORAX = "1:FB0|2:FH0R1,PA0R1C21->LC2_B22||";
    OD2P44  : LORAX = "1:FB2|2:FH2R2,PA6R2C6->LC7_C7||";
    OD3P42  : LORAX = "1:FB3|2:FH3R1,PA5R1C20->LC5_B21||";
    LC5_A1  : LORAX = "1:MSW4R0C0,G50R0->OH12R0P18|";
    LC2_B22 : LORAX = "1:MSW2R1C20,HHR1R1->OH2R1P66|";
    LC7_C7  : LORAX = "1:MSW6R2C7,HHL32R2->OH14R2P30|";
    LC5_B21 : LORAX = "1:MSW4R1C20,HHR43R1->OH4R1P65|";
    LC4_A20 : LORAX = "1:MSW3R0C19,HHR13R0->OH3R0P71|";
	LC5_A1  : LORAX2 = "OD5P43, X, X, X";
	LC2_B22 : LORAX2 = "OD0P84, X, X, X";
	LC7_C7  : LORAX2 = "OD2P44, X, X, X";
	LC5_B21 : LORAX2 = "OD3P42, X, X, X";
	LC4_A20 : LORAX2 = "OD1P2, X, X, X";
END;