disp.rpt
来自「VHDL电子抢答器的实现。有多个文件」· RPT 代码 · 共 599 行 · 第 1/2 页
RPT
599 行
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Device-Specific Information: d:\111\disp.rpt
disp
** EQUATIONS **
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _LC1_B19;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC5_B19;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _LC6_B11;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _LC8_B2;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _LC1_B11;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = _LC3_B19;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = _LC4_B2;
-- Node name is ':353'
-- Equation name is '_LC4_B19', type is buried
_LC4_B19 = LCELL( _EQ001);
_EQ001 = !d0 & !d1 & d2 & !d3;
-- Node name is ':377'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ002);
_EQ002 = !d0 & d1 & !d2 & !d3;
-- Node name is ':389'
-- Equation name is '_LC1_B2', type is buried
!_LC1_B2 = _LC1_B2~NOT;
_LC1_B2~NOT = LCELL( _EQ003);
_EQ003 = d1
# d2
# !d0
# d3;
-- Node name is ':401'
-- Equation name is '_LC2_B2', type is buried
!_LC2_B2 = _LC2_B2~NOT;
_LC2_B2~NOT = LCELL( _EQ004);
_EQ004 = d1
# d2
# d0
# d3;
-- Node name is ':404'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = LCELL( _EQ005);
_EQ005 = !d0 & d1 & d2
# d1 & !d3
# d0 & d2 & !d3
# !d1 & !d2 & d3
# !d0 & !d2 & !d3;
-- Node name is '~440~1'
-- Equation name is '~440~1', location is LC8_B19, type is buried.
-- synthesized logic cell
_LC8_B19 = LCELL( _EQ006);
_EQ006 = d0 & d1 & d2 & !d3
# !d1 & !d2;
-- Node name is ':440'
-- Equation name is '_LC3_B19', type is buried
_LC3_B19 = LCELL( _EQ007);
_EQ007 = _LC8_B19
# _LC4_B19
# _LC2_B19;
-- Node name is '~467~1'
-- Equation name is '~467~1', location is LC4_B11, type is buried.
-- synthesized logic cell
!_LC4_B11 = _LC4_B11~NOT;
_LC4_B11~NOT = LCELL( _EQ008);
_EQ008 = d3
# d0 & !d1
# !d1 & !d2
# !d0 & !d2
# !d0 & d1
# d0 & d2
# d1 & d2;
-- Node name is '~467~2'
-- Equation name is '~467~2', location is LC8_B11, type is buried.
-- synthesized logic cell
_LC8_B11 = LCELL( _EQ009);
_EQ009 = !d1 & !d2 & d3
# d0 & d2 & !d3
# d1 & d2 & !d3;
-- Node name is ':476'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ010);
_EQ010 = !_LC7_B11
# !_LC2_B11 & _LC8_B11
# !_LC2_B11 & _LC4_B11;
-- Node name is ':497'
-- Equation name is '_LC6_B19', type is buried
_LC6_B19 = LCELL( _EQ011);
_EQ011 = d0 & !d1 & d2 & !d3
# !d0 & d1 & d2 & !d3
# !d1 & !d2 & d3;
-- Node name is ':512'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = LCELL( _EQ012);
_EQ012 = d1 & !d2 & !d3
# !d0 & !d2 & !d3
# d0 & !d1 & d2 & !d3
# !d0 & d1 & !d3
# !d0 & !d1 & !d2
# !d1 & !d2 & d3;
-- Node name is ':542'
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = LCELL( _EQ013);
_EQ013 = _LC2_B11
# _LC3_B11 & !_LC4_B11;
-- Node name is '~544~1'
-- Equation name is '~544~1', location is LC3_B11, type is buried.
-- synthesized logic cell
_LC3_B11 = LCELL( _EQ014);
_EQ014 = !d0 & !d1 & !d2 & d3
# !d0 & d1 & d2 & !d3;
-- Node name is ':548'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = LCELL( _EQ015);
_EQ015 = !_LC1_B2 & _LC5_B11
# _LC2_B2;
-- Node name is ':572'
-- Equation name is '_LC7_B19', type is buried
_LC7_B19 = LCELL( _EQ016);
_EQ016 = _LC4_B19
# _LC6_B19;
-- Node name is ':584'
-- Equation name is '_LC5_B19', type is buried
_LC5_B19 = LCELL( _EQ017);
_EQ017 = !_LC1_B2 & !_LC2_B19 & _LC7_B19
# _LC2_B2;
-- Node name is '~614~1'
-- Equation name is '~614~1', location is LC2_B19, type is buried.
-- synthesized logic cell
_LC2_B19 = LCELL( _EQ018);
_EQ018 = d1 & !d2 & !d3;
-- Node name is '~622~1'
-- Equation name is '~622~1', location is LC7_B11, type is buried.
-- synthesized logic cell
!_LC7_B11 = _LC7_B11~NOT;
_LC7_B11~NOT = LCELL( _EQ019);
_EQ019 = _LC1_B2
# _LC2_B2;
-- Node name is ':622'
-- Equation name is '_LC1_B19', type is buried
_LC1_B19 = LCELL( _EQ020);
_EQ020 = !_LC1_B2 & !_LC2_B2 & _LC2_B19
# !_LC1_B2 & !_LC2_B2 & _LC7_B19;
Project Information d:\111\disp.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,318K
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