count10.tdf

来自「VHDL电子抢答器的实现。有多个文件」· TDF 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; 
entity count10 is
           port( clk:in std_logic; --1hz
                 en:in std_logic;
                 clr:in std_logic;
                 up,dn:in std_logic;
                 dout:out std_logic_vector(3 downto 0)
                 );
end count10; 
architecture behav of count10 is
signal q:integer range 0 to 9;
begin
process(clk,clr)
begin
          if clr='1' then q<=3;
          elsif clk'event and clk='1' then
          if en='1' then
          if up='1' then 
          if q<9 then q<=q+1;
          else q<=3;end if;
elsif dn='1' then
if q>0 then q<=q-1;
else q<=3;end if;
end if;
end if;
end if;
end process;
dout<=conv_std_logic_vector (q,4);
end behav;