jiajianfen1.rpt
来自「VHDL电子抢答器的实现。有多个文件」· RPT 代码 · 共 606 行 · 第 1/2 页
RPT
606 行
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\qingdaqi1\jiajianfen1.rpt
jiajianfen1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: d:\qingdaqi1\jiajianfen1.rpt
jiajianfen1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clr
Device-Specific Information: d:\qingdaqi1\jiajianfen1.rpt
jiajianfen1
** EQUATIONS **
clk : INPUT;
clr : INPUT;
en : INPUT;
ff : INPUT;
zf : INPUT;
-- Node name is 'fen0'
-- Equation name is 'fen0', type is output
fen0 = q0;
-- Node name is 'fen1'
-- Equation name is 'fen1', type is output
fen1 = q1;
-- Node name is 'fen2'
-- Equation name is 'fen2', type is output
fen2 = q2;
-- Node name is 'fen3'
-- Equation name is 'fen3', type is output
fen3 = q3;
-- Node name is ':13' = 'q0'
-- Equation name is 'q0', location is LC4_A15, type is buried.
!q0 = q0~NOT;
q0~NOT = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = !_LC8_A20 & !q0
# !en & !q0
# en & !_LC8_A20;
-- Node name is ':12' = 'q1'
-- Equation name is 'q1', location is LC1_A23, type is buried.
q1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = en & _LC4_A23
# !en & q1;
-- Node name is ':11' = 'q2'
-- Equation name is 'q2', location is LC5_A23, type is buried.
!q2 = q2~NOT;
q2~NOT = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = !_LC6_A23 & !_LC8_A23 & !q2
# !en & !q2
# en & !_LC6_A23 & !_LC8_A23;
-- Node name is ':10' = 'q3'
-- Equation name is 'q3', location is LC2_A20, type is buried.
q3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = en & _LC6_A20
# en & _LC7_A20
# !en & q3;
-- Node name is '|LPM_ADD_SUB:97|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = LCELL( _EQ005);
_EQ005 = q0 & q1;
-- Node name is '|LPM_ADD_SUB:97|addcore:adder|:75' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = LCELL( _EQ006);
_EQ006 = !q0 & q1
# q0 & !q1;
-- Node name is ':63'
-- Equation name is '_LC1_A20', type is buried
_LC1_A20 = LCELL( _EQ007);
_EQ007 = !q3
# _LC5_A20;
-- Node name is ':65'
-- Equation name is '_LC5_A20', type is buried
!_LC5_A20 = _LC5_A20~NOT;
_LC5_A20~NOT = LCELL( _EQ008);
_EQ008 = q2
# q1
# q0;
-- Node name is ':161'
-- Equation name is '_LC4_A20', type is buried
_LC4_A20 = LCELL( _EQ009);
_EQ009 = q3
# !_LC5_A20;
-- Node name is ':231'
-- Equation name is '_LC7_A23', type is buried
!_LC7_A23 = _LC7_A23~NOT;
_LC7_A23~NOT = LCELL( _EQ010);
_EQ010 = _LC4_A20 & !q0 & !q1 & q2
# _LC4_A20 & q1 & !q2
# _LC4_A20 & q0 & !q2;
-- Node name is '~266~1'
-- Equation name is '~266~1', location is LC3_A20, type is buried.
-- synthesized logic cell
_LC3_A20 = LCELL( _EQ011);
_EQ011 = !q3 & zf
# _LC5_A20 & zf;
-- Node name is ':266'
-- Equation name is '_LC7_A20', type is buried
_LC7_A20 = LCELL( _EQ012);
_EQ012 = _LC3_A20 & !q2 & q3
# !_LC1_A15 & _LC3_A20 & q3
# _LC1_A15 & _LC3_A20 & q2 & !q3;
-- Node name is ':267'
-- Equation name is '_LC6_A20', type is buried
_LC6_A20 = LCELL( _EQ013);
_EQ013 = !_LC5_A20 & q3 & !zf
# !ff & q3 & !zf;
-- Node name is ':275'
-- Equation name is '_LC6_A23', type is buried
!_LC6_A23 = _LC6_A23~NOT;
_LC6_A23~NOT = LCELL( _EQ014);
_EQ014 = _LC1_A15 & _LC1_A20 & q2
# !_LC1_A15 & _LC1_A20 & !q2
# !zf;
-- Node name is ':276'
-- Equation name is '_LC8_A23', type is buried
!_LC8_A23 = _LC8_A23~NOT;
_LC8_A23~NOT = LCELL( _EQ015);
_EQ015 = !_LC7_A23 & !q2
# !ff & !q2
# ff & !_LC7_A23
# zf;
-- Node name is ':280'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = LCELL( _EQ016);
_EQ016 = _LC4_A20 & q0 & q1
# ff & _LC4_A20 & !q0 & !q1
# !ff & q1;
-- Node name is ':283'
-- Equation name is '_LC4_A23', type is buried
_LC4_A23 = LCELL( _EQ017);
_EQ017 = _LC2_A23 & _LC3_A20
# _LC3_A23 & !zf;
-- Node name is ':292'
-- Equation name is '_LC8_A20', type is buried
!_LC8_A20 = _LC8_A20~NOT;
_LC8_A20~NOT = LCELL( _EQ018);
_EQ018 = q0 & !q3 & zf
# ff & q0 & !q3
# ff & q0 & !zf
# !ff & !q0 & !zf;
Project Information d:\qingdaqi1\jiajianfen1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,276K
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