zhonghe2.vhd

来自「VHDL电子抢答器的实现。有多个文件」· VHDL 代码 · 共 43 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY zhonghe2 IS
PORT(
		CP,clr,zf,ff  :IN STD_LOGIC; 
		SEGOUT	:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		SELOUT 	:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
		d1,d2,d3,d4 ,djs,fen:in std_logic_vector(3 downto 0)
	);--djs是到抢答的限制时间
END zhonghe2;


ARCHITECTURE A OF zhonghe2 IS

SIGNAL Q :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL f1 :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL f2 :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL f3 :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL f4 :STD_LOGIC_VECTOR(2 DOWNTO 0);




BEGIN
		f1<=5;--给初值
		f2<=5;
		f3<=5;
		f4<=5;

PROCESS(CP,clr,zf,ff)
	BEGIN
		IF CP'EVENT AND CP = '1' THEN
			Q <= Q+1;
		END IF;

        
fen   <= f1 WHEN d1 = "0001" ELSE
		 f2 WHEN d1 = "0010" ELSE
		 f3 WHEN d1 = "0011" ELSE
		 f4 WHEN d1 = "0100" 			

		if clr=1 then--清零键无